PRELIMINARY

Revision 2.0

- 2 -

April 2000

CCPCCCRCELIMINARY

Preliminary

PRELIMINARY

K6R1004V1C-C/C-L, K6R1004V1C-I/C-P

CMOS SRAM

256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 10,12,15,20ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 30mA(Max.)

(CMOS) : 5mA(Max.)

0.5mA(Max.) L-Ver. only

Operating K6R1004V1C-10 : 75mA(Max.)

K6R1004V1C-12 : 70mA(Max.)

K6R1004V1C-15 : 68mA(Max.)

K6R1004V1C-20 : 65mA(Max.)

• Single 3.3

±0.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Mimimum Data Retention ; L-ver. Only

• Center Power/Ground Pin Configuration

• Standard Pin Configuration :

K6R1004V1C-J : 32-SOJ-400

The K6R1004V1C is a 1,048,576-bit high-speed Static Random

Access Memory organized as 262,144 words by 4 bits. The

K6R1004V1C uses 4 common input and output lines and has

an output enable pin which operates faster than address

access time at read cycle. The device is fabricated using SAM-

SUNG

′s advanced CMOS process and designed for high-

speed circuit technology. It is particularly well suited for use in

high-density

high-speed

system

applications.

The

K6R1004V1C is packaged in a 400 mil 32-pin plastic SOJ.

PIN FUNCTION

Pin Name

Pin Function

Address Inputs

WE

Write Enable

CS

Chip Select

OE

Output Enable

Data Inputs/Outputs

Power(+3.3V)

Ground

N.C

No Connection

Clk Gen.

CS

WE

OE

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

512x4 Columns

I/O Circuit &

SOJ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

Vss

Vcc

N.C

N.C

CS

Vcc

Vss

WE

N.C

K6R1004V1C-C10/C12/C15/C20

Commercial Temp.

K6R1004V1C-I10/I12/I15/I20

Industrial Temp.

ORDERING INFORMATION