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IDT70V5378S200BG Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT70V5378S200BG Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 29 page 6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges 7 External Address Previous Internal Address Internal Address Used CLK CNTLD CNTINC CNTRST MKLD I/O MODE XX 0 ↑ XX L(3) XDI/O(0) Counter Reset to Address 0 An Ap Ap ↑ XX H L DI/O(p) Counter disabled (Ap reused) An X An ↑ L(3) XH H DI/O (n) External Address Used An Ap Ap ↑ HH H H DI/O(p) External Address Blocked—Counter disabled (Ap reused) XAp Ap + 1(5) ↑ H L(4) HH DI/O(p+1)(5) Counter Enabled—Internal Address generation 5649 tbl 04 Truth Table II—Address Counter & Mask Control(1,2) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, LB, UB and OE. 3. CNTLD and CNTRST are independent of all other memory control signals including CE0, CE1 and LB, UB. 4. The address counter advances if CNTINC = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, LB, UB. 5. The counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle). OE CLK CE0 CE1 UB LB R/W Upper Byte I/O9-17 Lower Byte I/O0-8 MODE X ↑ H X X X X High-Z High-Z Deselected–Power Down X ↑ X L X X X High-Z High-Z Deselected–Power Down X ↑ L H H H X High-Z High-Z All Bytes Deselected X ↑ LH H L L High-Z DIN Write to Lower Byte Only X ↑ LH L H L DIN High-Z Write to Upper Byte Only X ↑ LH L L L DIN DIN Write to Both Bytes L ↑ LH H L H High-Z DOUT Read Lower Byte Only L ↑ LH L H H DOUT High-Z Read Upper Byte Only L ↑ LH L L H DOUT DOUT Read Both Bytes H ↑ X X X X X High-Z High-Z Outputs Disabled 5649 tbl 03 Truth Table I—Read/Write and Enable Control(1,2,3) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CNTLD, CNTINC, CNTRST = VIH. 3. OE is an asynchronous input signal. |
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