10

COMMERCIALTEMPERATURERANGE

IDT72V70800 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 512

TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS

NOTE:

1. n denotes an input stream number from 0 to 3.

Description

OFn2, OFn1, OFn0

These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to

(Offset Bits 2, 1 & 0)

start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse

input signal is applied to the

F0i input of the device. See Figure 5.

DLEn

(Data Latch Edge)

DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.

DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.

GCI mode:

DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.

DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.

Read/Write Address:

Reset Value:

15

14

13

12

11

10

9876543210

OF32

OF31

OF30

DLE3

OF22

OF21

OF20

DLE2

OF12

OF11

OF10

DLE1

OF02

OF01

OF00

DLE0

FOR Register