7

IDT72V70800 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 512 x 512

COMMERCIALTEMPERATURERANGE

TABLE 4 — OUTPUT HIGH IMPEDANCE CONTROL

TABLE 3 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING

TABLE 2 — CONSTANT THROUGHPUT

DELAY VALUE

TABLE 1 — VARIABLE THROUGHPUT

DELAY VALUE

NOTE:

1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.

Delay for Variable Throughput Delay Mode

Input Rate

(m – output channel number)

(n – input channel number)

m < n

m = n, n+1, n+2

m > n+2

8.192 Mb/s 128 – (n-m) time-slots m-n + 128 time-slots m-ntime-slots

Delay for Constant Throughput Delay Mode

Input Rate

(m – output channel number)

(n – input channel number)

8.192 Mb/s

128 + (128 – n) + m time-slots

A6

A5

A4

A3

A2

A1

A0

Location

0

000

0000

Control Register, CR

0

000

0001

Interface Mode Selection Register, IMS

0

000

0010

Frame Alignment Register, FAR

0

000

0011

Frame Input Offset Register, FOR

1

000

0000

Ch0

1

000

0001

Ch1

1

0

0

.

....

.

1

001

1110

Ch30

1

001

1111

Ch31

1

010

0000

Ch32

1

010

0001

Ch33

1

0

1

.

....

.

1

011

1110

Ch62

1

011

1111

Ch63

1

100

0000

Ch64

1

100

0001

Ch65

1

1

0

.

....

.

1

111

1110

Ch126

1

111

1111

Ch127

OE bit in Connection

ODE pin

OSB bit in IMS

TX Output Driver

Memory

Register

Status

0

Don’t Care

Don’t Care

Per Channel

High-Impedance

1

0

0

High-Impedance

1

0

1

Enable

1

1

1

Enable

1

1

0

Enable