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IDT70V5388S166BC Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT70V5388S166BC Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 29 page  6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges 5 Pin Definitions Port 1 Port 2 Port 3 Port 4 Description A0P1 - A15P1(1) A0P2 - A15P2(1) A0P3 - A15P3(1) A0P4 - A15P4(1) Address Inputs. In the CNTRD and MKRD operations, these pins serve as outputs for the internal address counter and the internal counter mask register respectively. I/O0P1 - I/O17P1 I/O0P2 - I/O17P2 I/O0P3 - I/017P3 I/O0P4 - I/O17P4 Data Bus Input/Output. CLKP1 CLKP2 CLKP3 CLKP4 Clock Input. The maximum clock input rate is fMAX. The clock signal can be free running or strobed depending on system requirements. MRST Master Reset Input. MRST is an asycnchronous input, and affects all ports. It must be asserted LOW (MRST = VIL) at initial power-up. Master Reset sets the internal value of all address counters to zero, and sets the counter mask registers for each port to 'unmasked'. It also resets the output flags for the mailboxes and the counter interrupts (INT = CNTINT = VIH) and deselects all registered control signals. CE0P1 , CE1P1 CE0P2 , CE1P2 CE0P3 , CE1P3 CE0P4 , CE1P4 Chip Enable Inputs. To activate any port, both signals must be asserted to their active states (CE0 = VIL, CE1 = VIH). A given port is disabled if either chip enable is deasserted (CE0 = VIH and/or CE1 = VIL). R/WPI R/WP2 R/WP3 R/WP4 Read/Write Enable Input. This signal is asserted LOW (R/ W = VIL) in order to write to the FourPort memory array, and it is asserted HIGH (R/W = VIH) in order to read from the array. LBP1 LBP2 LBP3 LBP4 Lower Byte Select Input (I/O0 - I/O8). Asserting this signal LOW (LB = VIL) enables read/write operations to the lower byte. For read operations, this signal is used in conjunction with OE in order to drive output data on the lower byte of the data bus. UBP1 UBP2 UBP3 UBP4 Upper Byte Select Input (I/O9 - I/O17). Asserting this signal LOW (LB = VIL) enables read/write operations to the upper byte. For read operations, this signal is used in conjunction with OE in order to drive output data on the upper byte of the data bus. OEP1 OEP2 OEP3 OEP4 Output Enable Input. Asserting this signal LOW (OE = VIL) enables the device to drive data on the I/O pins during read operation. OE is an asychronous input. CNTLDP1 CNTLDP2 CNTLDP3 CNTLDP4 Counter Load Input. Asserting this signal LOW (CNTLD = VIL) loads the address on the address lines (A0 - A15(1)) into the internal address counter for that port. CNTINCP1 CNTINCP2 CNTINCP3 CNTINCP4 Counter Increment Input. Asserting this signal LOW (CNTINC = VIL) increments the internal address counter for that port on each rising edge of the clock signal. The counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle). CNTRDP1 CNTRDP2 CNTRDP3 CNTRDP4 Counter Readback Input. When asserted LOW (CNTRD = VIL) causes that port to output the value of its internal address counter on the address lines for that port. Counter readback is independent of the chip enables for that port. If the port is activated (CE0 = VIL and CE1 = VIH), during the counter readback operation, then the data bus will output the data associated with that readback address in the FourPort memory array (assuming that the byte enables and output enables are also asserted). Truth Table III indicates the required states for all other counter controls during this operation. The specific operation and timing of this funcion is described in detail in the text. CNTRSTP1 CNTRSTP2 CNTRSTP3 CNTRSTP4 Counter Reset Input. Asserting this signal LOW (CNTRST = VIL) resets the address counter for that port to zero. CNTINTP1 CNTINTP2 CNTINTP3 CNTINTP4 Counter Interrupt Flag Output. This signal is asserted LOW (CNTINT = VIL) when the internal address counter for that port 'wraps around' from max address [(the counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle)] to address min. as the result of counter increment (CNTINT = VIL). The signal goes LOW for one clock cycle, then automatically resets. 5649 tbl 01 |
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