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IDT70V5388S133BGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70V5388S133BGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 29 page  1 ©2003 Integrated Device Technology, Inc. AUGUST 2003 DSC-5649/3 Port - 1 Logic Block Diagram(2) ◆ Counter readback on address lines ◆ Mask register readback on address lines ◆ Global Master reset for all ports ◆ Dual Chip Enables on all ports for easy depth expansion ◆ Separate upper-word and lower-word controls on all ports ◆ 272-BGA package (27mm x 27mm 1.27mm ball pitch) and 256-BGA package (17mm x 17mm 1.0mm ball pitch) ◆ Commercial and Industrial temperature ranges ◆ JTAG boundary scan ◆ MBIST (Memory Built-In Self Test) controller Features ◆ True four-ported memory cells which allow simultaneous access of the same memory location ◆ Synchronous Pipelined device – 64/32K x 18 organization ◆ Pipelined output mode allows fast 200MHz operation ◆ High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x 4 ports) ◆ LVTTL I/O interface ◆ High-speed clock to data access 3.0ns (max.) ◆ 3.3V Low operating power ◆ Interrupt flags for message passing ◆ Width and depth expansion capabilities 3.3V 64/32K X 18 SYNCHRONOUS FOURPORT™ STATIC RAM IDT70V5388/78 NOTE: 1. A15x is a NC for IDT70V5378. 2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks. TMS TCK TDI CLKMBIST TDO JTAG Controller MBIST TRST 64KX18 Memory Array Port 1 Address Decode , Port 1 Interrupt Logic INTP1 Priority Decision Logic Port 1 Counter/ Address Register Port 1 Mask Register Port 1 Readback Register Addr. Read Back R/ WP1 CE0P1 CE1P1 CLKP1 MRST Port 1 I/O Control R/ WP1 UBP1 CE0P1 CE1P1 LBP1 OEP1 I/O9P1 - I/O17P1 I/O0P1 - I/O8P1 CLKP1 MRST CNTINTP1 0 1 1/0 MRST A0P1 -A15P1(1) CNTRDP1 MKRDP1 MKLDP1 CNTINCP1 CNTLDP1 CNTRSTP1 5649 drw 01 ◆ Counter wrap-around control – Internal mask register controls counter wrap-around – Counter-Interrupt flags to indicate wrap-around |
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