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M41T81SMY6F Datasheet(PDF) 8 Page - STMicroelectronics |
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M41T81SMY6F Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 29 page M41T81S 8/29 READ Mode In this mode the master reads the M41T81S slave after setting the slave address (see Figure 9., page 9). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave ad- dress are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master trans- mitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41T81S slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to “An+2.” This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h). Note: This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implement- ed whereby the master reads the M41T81S slave without first writing to the (volatile) address point- er. The first address that is read is the last one stored in the pointer (see Figure 10., page 9). Figure 8. Slave Address Location AI00602 R/W SLAVE ADDRESS START A 0 100 0 11 |
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