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K4S64323LF-DP75-PB Datasheet(PDF) 7 Page - Samsung semiconductor |
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K4S64323LF-DP75-PB Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 8 page K4S64323LF-S(D)N/U/P Rev. 1.5 Dec 2002 CMOS SDRAM AC CHARACTERISTICS(AC operating conditions unless otherwise noted) Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Parameter Symbol - 75 -1H -1L - 15 Unit Note Min Max Min Max Min Max Min Max CLK cycle time CAS latency=3 tCC 7.5 1000 9.5 1000 9.5 1000 15 1000 ns 1 CAS latency=2 9.5 9.5 12 15 CAS latency=1 - - 25 30 CLK to valid output delay CAS latency=3 tSAC 5.4 7 7 9 ns 1,2 CAS latency=2 7 7 8 9 CAS latency=1 - - 20 24 Output data hold time CAS latency=3 tOH 2.5 2.5 2.5 2.5 ns 2 CAS latency=2 2.5 2.5 2.5 2.5 CAS latency=1 - - 2.5 2.5 CLK high pulse width tCH 2.5 3 3 3.5 ns 3 CLK low pulse width tCL 2.5 3 3 3.5 ns 3 Input setup time tSS 2.0 2.5 2.5 3.5 ns 3 Input hold time tSH 1.0 1.5 1.5 2.0 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ 5.4 7 7 9 ns CAS latency=2 7 7 8 9 CAS latency=1 - - 20 24 Notes : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. |
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