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K4S64323LF-DN15-PB Datasheet(PDF) 2 Page - Samsung semiconductor |
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K4S64323LF-DN15-PB Datasheet(HTML) 2 Page - Samsung semiconductor |
2 / 8 page K4S64323LF-S(D)N/U/P Rev. 1.5 Dec 2002 CMOS SDRAM The K4S64323LF is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabri- cated with SAMSUNG ′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. • 2.5V Power Supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • All inputs are sampled at the positive going edge of the system clock . • Burst read single-bit write operation. • DQM for masking. • Auto & self refresh. • 64ms refresh period (4K cycle). • Extended temperature range (-25 °C to 85°C). Industrial Temperature range (-40 °C to 85°C) for low power. • 90balls FBGA( -SXXX -Pb, -DXXX -Pb Free). GENERAL DESCRIPTION FEATURES 512K x 32Bit x 4 Banks SDRAM FUNCTIONAL BLOCK DIAGRAM Samsung Electronics reserves the right to change products or specification without notice. * Bank Select Data Input Register 512K x 32 512K x 32 Column Decoder Latency & Burst Length Programming Register LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE DQM LWE LDQM DQi CLK ADD LCAS LWCBR 512K x 32 512K x 32 Timing Register ORDERING INFORMATION -S(D)N ; Low Power, Operating Temp : -25 °C~85°C. -S(D)U ; Super Low Power, Operating Temp : -25 °C~85°C. -S(D)P ; Low Power, Operating Temp : -40 °C~85°C. Notes : 1. In case of 55MHz Frequency, CL1 can be supported. 2. In case of 40MHz Frequency, CL1 can be supported. 3. In case of 33MHz Frequency, CL1 can be supported. Part No. Max Freq. Interface Package K4S64323LF-S(D)N/U/P75 133MHz(CL=3)*1 105MHz(CL=2) LVCMOS 90FBGA Pb (Pb Free) K4S64323LF-S(D)N/U/P1H 105MHz(CL=2) K4S64323LF-S(D)N/U/P1L 105MHz(CL=3)*2 K4S64323LF-S(D)N/U/P15 66MHz(CL=2/3)*3 |
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