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IDT54FCT573ATPGB Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT54FCT573ATPGB Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 7 page MILITARYANDINDUSTRIALTEMPERATURERANGES IDT54/74FCT573T/AT/CT FASTCMOSOCTALTRANSPARENTLATCH 1 JUNE 2002 MILITARY AND INDUSTRIAL TEMPERATURE RANGES The IDT logo is a registered trademark of Integrated Device Technology, Inc. © 2002 Integrated Device Technology, Inc. DSC-5948/3 FEATURES: • Std., A, and C grades • Low input and output leakage ≤≤≤≤≤1µA (max.) • CMOS power levels • True TTL input and output compatibility: –VOH = 3.3V (typ.) –VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) • Power off disable outputs permit "live insertion" • Available in the following packages: – Industrial: SOIC, SSOP, QSOP, TSSOP – Military: CERDIP, LCC FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH DESCRIPTION: The FCT573Tis an octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to thedatawhenLatchEnable(LE)ishigh. WhenLEislow,thedatathatmeets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bus output is in the high-impedance state. LE D G O O0 D0 D G O O1 D1 D G O O2 D2 D G O O3 D3 D G O O4 D4 D G O O5 D5 D G O O6 D6 D G O O7 D7 OE |
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