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74AUP1G32GW Datasheet(PDF) 4 Page - NXP Semiconductors |
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74AUP1G32GW Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 16 page 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 4 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 8. Functional description 8.1 Function table [1] H = HIGH voltage level; L = LOW voltage level. 9. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP5 packages: above 87.5 °C the value of P tot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of P tot derates linearly with 2.4 mW/K. Table 5: Function table [1] Input Output A B Y LL L LH H HL H HH H Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +4.6 V IIK input clamping current VI <0V - −50 mA VI input voltage [1] −0.5 +4.6 V IOK output clamping current VO >VCC or VO <0V - ±50 mA VO output voltage active mode [1] −0.5 VCC + 0.5 V Power-down mode [1] −0.5 +4.6 V IO output current VO =0 VtoVCC - ±20 mA ICC quiescent supply current - +50 mA IGND ground current - −50 mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C [2] - 250 mW |
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