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UPD78F4218AYGF-3BA Datasheet(PDF) 8 Page - NEC |
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UPD78F4218AYGF-3BA Datasheet(HTML) 8 Page - NEC |
8 / 60 page Data Sheet U14125EJ1V0DS00 8 µµµµPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY 2. PIN CONFIGURATION (TOP VIEW) •••• 100-pin plastic LQFP (fine pitch) (14 ×××× 14) µµµµPD78F4216AGC-8EU, µµµµPD78F4218AGC-8EU, µµµµPD78F4216AYGC-8EU, µµµµPD78F4218AYGC-8EU Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 4. The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only. 5. The EXA pin is available in the µPD78F4218A, 78F4218AY only. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 76 P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 VDD X2 X1 VSS XT2 XT1 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AVDDNote 2 AVREF0 P10/ANI0 P62/A18 P61/A17 P60/A16 VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P84/A4 P83/A3 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 |
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