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DP8418D-80 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DP8418D-80 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 28 page  Pin Definitions (Continued) indicating that no hidden refresh was performed while RFCK was high When this pin is set low by an external gate the on-chip refresh counter is reset to all zeroes WIN Write Enable Input WE Write Enable Output - WE follows WIN unconditional- ly RAHS Row Address Hold Time Select - Selects the tRAH to be generated by the DP8419 delay line to allow use with fast or slow DRAMs CAS Column Address Strobe Output - In mode 5 and in mode 4 with CASIN low before RC goes low CAS goes low automatically after the column address is valid on the address outputs In mode 4 CAS follows CASIN directly af- ter RC goes low allowing for nibble accessing CAS is al- ways high during refresh RAS 0 – 3 Row Address Strobe Outputs - The enabled RAS output (see Table II) follows RASIN directly during an access During refresh all RAS outputs are enabled B0 B1 Bank Select Inputs - These pins are decoded to enable one of the four RAS outputs during an access (see Table I and Table II) TABLE I DP8417 DP8419 DP8419X Memory Bank Decode Bank Select (Strobed by ADS) Enabled RASn B1 B0 0 0 RAS0 0 1 RAS1 1 0 RAS2 1 1 RAS3 TABLE II DP8418 Memory Bank Decode Bank Select (Strobed by ADS) Enabled RASn B1 NC 0 X RAS0 and RAS1 1 X RAS2 and RAS3 Conditions for All Modes INPUT ADDRESSING The address block consists of a row-address latch a col- umn-address latch and a resettable refresh counter The address latches are fall-through when ADS is high and latch when ADS goes low If the address bus contains valid ad- dresses until after CAS goes low at the end of the memory cycle ADS can be permanently high Otherwise ADS must go low while the addresses are still valid DRIVE CAPABILITY The DP8419 has timing parameters that are specified driv- ing the typical capacitance (including traces) of 88 5V-only DRAMs Since there are 4 RAS outputs each is specified driving one-fourth of the total memory CAS WE and the address outputs are specified driving all 88 DRAMs The graph in Figure 10 may be used to determine the slight variations in timing parameters due to loading conditions other than 88 DRAMs Because of distributed trace capacitance and inductance and DRAM input capacitance current spikes can be creat- ed causing overshoots and undershoots at the DRAM in- puts that can change the contents of the DRAMs or even destroy them To reduce these spikes a damping resistor (low inductance carbon) should be inserted between the DP8419 outputs and the DRAMs as close as possible to the DP8419 The damping resistor values may differ de- pending on how heavily an output is loaded These resistors should be determined by the first prototypes (not wire- wrapped due to the larger distributed capacitance and in- ductance) Resistors should be chosen such that the tran- sition on the control outputs is critically damped Typical values will be from 15X to 100X with the lower values be- ing used with the larger memory arrays Note that AC pa- rameters are specified with 15X damping resistors For more information see AN-305 ‘‘Precautions to Take When Driving Memories’’ DP8419 DRIVING ANY 16k 64k or 256k DRAMs The DP8419 can drive any 16k 64k or 256k DRAMs All 16k DRAMs use basically the same configuration including the 5V-only version Hence in most applications different man- ufacturers’ DRAMs are interchangeable (for the same sup- ply-rail chips) and the DP8419 can drive them all (see Fig- ure 1a ) There are three basic configurations for the 5V-only 64k DRAMs a 128-row by 512-column array with an on-RAM refresh counter a 128-row by 512-column array with no on- RAM refresh counter and a 256-row by 256-column array with no on-RAM refresh counter The DP8419 can drive all three configurations and allows them all to be interchange- able (as shown in Figures 1b and 1c ) providing maximum flexibility in the choice of DRAMs Since the 9-bit on-chip refresh counter can be used as a 7-bit refresh counter for the 128-row configuration or as an 8-bit refresh counter for the 256-row configuration the on-RAM refresh counter if present is never used 256k DRAMs require all 18 of the DP8419’s address inputs to select one memory location within the DRAM RAS-only refreshing with the nine-bit refresh-counter on the DP8419 makes CAS before RAS refreshing available on 256k DRAMs unnecessary READ WRITE AND READ-MODIFY-WRITE CYCLES The output signal WE determines what type of memory access cycle the memory will perform If WE is kept high while CAS goes low a read cycle occurs If WE goes low before CAS goes low a write cycle occurs and data at DI (DRAM input data) is written into the DRAM as CAS goes low If WE goes low later than tCWD after CAS goes low first a read occurs and DO (DRAM output data) becomes valid then data DI is written into the same address in the DRAM as WE goes low In this read-modify-write case DI and DO cannot be linked together WE always follows WIN directly to determine the type of access to be performed POWER-UP INITIALIZE When VCC is first applied to the DP8419 an initialize pulse clears the refresh counter and the internal control flip-flops 7 |
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