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EPC8QI100 Datasheet(PDF) 6 Page - Altera Corporation |
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EPC8QI100 Datasheet(HTML) 6 Page - Altera Corporation |
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6 / 36 page  2–6 Altera Corporation Configuration Handbook, Volume 2 August 2005 Functional Description f For detailed information on using these schemes to configure your Altera FPGA, refer to the appropriate FPGA family chapter in the Configuration Handbook. Configuration Signals Table 2–3 lists the configuration signal connections between the enhanced configuration device and Altera FPGAs. Table 2–3. Configuration Signals Enhanced Configuration Device Pin Altera FPGA Pin Description DATA[] DATA[] Configuration data transmitted from the configuration device to the FPGA, which is latched on the rising edge of DCLK. DCLK DCLK Configuration device generated clock used by the FPGA to latch configuration data provided on the DATA[] pins. nINIT_CONF nCONFIG Open-drain output from the configuration device that is used to initiate FPGA reconfiguration using the initiate configuration (INIT_CONF) JTAG instruction. This connection is not needed if the INIT_CONF JTAG instruction is not needed. If nINIT_CONF is not connected to nCONFIG, nCONFIG must be tied to VCC either directly or through a pull-up resistor. OE nSTATUS Open-drain bidirectional configuration status signal, which is driven low by either device during POR and to signal an error during configuration. Low pulse on OE resets the enhanced configuration device controller. nCS CONF_DONE Configuration done output signal driven by the FPGA. |
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