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M5M564R16DTP-15 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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M5M564R16DTP-15 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
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1 / 7 page  M5M564R16DJ,TP-10,-12,-15 MITSUBISHI LSIs 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM MITSUBISHI ELECTRIC 1 Outline 44P0K(J) 44P3W-H(TP) PIN CONFIGURATION (TOP VIEW) 1998.6.18 Ver.A PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. APPLICATION FEATURES High-speed memory system 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DQ1 GND 17 18 19 20 21 22 S W 32 31 30 29 28 27 26 25 24 23 OE GND N.C 36 35 34 33 41 40 39 38 37 44 43 42 LB UB ADDRESS INPUTS CHIP SELECT INPUTS (3.3V) (0V) (3.3V) (0V) DATA INPUTS/ OUTPUTS DATA INPUTS/ OUTPUTS WRITE CONTROL INPUT ADDRESS INPUTS ADDRESS INPUTS DATA INPUTS/ OUTPUTS DATA INPUTS/ OUTPUTS BYTE CONTROL INPUTS OUTPUT ENABLE INPUT ADDRESS INPUTS A0 A1 A2 A3 A4 A15 A14 A13 DQ2 DQ4 DQ16 DQ15 DQ14 DQ13 DQ3 VCC VCC DQ5 DQ6 DQ8 DQ7 DQ12 DQ11 DQ10 DQ9 A5 A6 A7 A8 A12 A11 A10 A9 DESCRIPTION The M5M564R16D is a family of 65536-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by LB and UB. The operation mode of the M5M564R16D is determined by a combination of the device control inputs S, W, OE, LB, and UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with low level LB and/or low level UB and low level S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of W, LB, UB or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while LB and/or UB and S are in an active state. (LB and/or UB=L, S=L) When setting LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upper- Byte are in a non-selectable mode. When setting LB and UB at a high level or S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by LB, UB and S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. FUNCTION N.C N.C PACKAGE M5M564R16DJ M5M564R16DTP : 44pin 400mil SOJ : 44pin 400mil TSOP(II) •Fast access time M5M564R16DJ,TP-10 ... 10ns(max) M5M564R16DJ,TP-12 ... 12ns(max) M5M564R16DJ,TP-15 ... 15ns(max) •Low power dissipation Active .................. 363mW(typ) •Single +3.3V power supply •Fully static operation : No clocks, No refresh •Common data I/O •Easy memory expansion by S •Three-state outputs : OR-tie capability •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs •Separate control of lower and upper bytes by LB and UB |
Similar Part No. - M5M564R16DTP-15 |
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Similar Description - M5M564R16DTP-15 |
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