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CS6403-IQ Datasheet(PDF) 6 Page - Cirrus Logic

Part No. CS6403-IQ
Description  Echo-Cancelling Codec
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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SWITCHING CHARACTERISTICS (TA = 25°C; AVDD and DVDD = +5V, output loaded with
30 pF; Input Levels: Logic 0 = 0V, Logic 1 = DVDD)
Parameter
Symbol
Min
Typ
Max
Units
Mode 1 - MASTER
Input clock (CLKIN) frequency
CLKIN
7.78
8.192
8.60
MHz
CLKIN low time
tckl
30
-
-
ns
CLKIN high time
tckh
30
-
-
ns
Sample Rate
Fs
-
8
-
kHz
SCLK and SYNCOUT output delay from CLKIN rising
tpd3
-
-
50
ns
SCLK duty cycle
(Note 12)
tsckw
-50
-
%
SCLK rising to SYNCOUT rising
tsr1
-12
30
ns
SCLK rising to SYNCOUT falling
tsf1
-
6
30
ns
SDO delay from SCLK edge
tpd1
-
-
70
ns
SDI setup time to SCLK edge
ts1
15
-
-
ns
SDI hold time from SCLK edge
th1
10
-
-
ns
SDO to Hi-Z state
thz
-
-
50
ns
SDO to non-Hi-Z
bit 1
tnz
5-
-
ns
RESET pulse width high
250
-
-
µs
Mode 2 - SLAVE
Input clock (SCLK) frequency
SCLK
243
0.97
1.95
256
1.024
2.048
268
1.08
2.15
kHz
MHz
MHz
SCLK low time
tckl
150
-
-
ns
SCLK high time
tckh
150
-
-
ns
SYNCOUT output delay from SSYNC rising
tpdsr
-
-
50
ns
SYNCOUT output delay from SSYNC falling
tpdsf
-
-
50
ns
Sample Rate
Fs
-
8
-
kHz
SDI/SSYNC setup time to SCLK edge
ts1
15
-
-
ns
SDI/SSYNC hold time from SCLK edge
th1
10
-
-
ns
SDO delay from SCLK edge
tpd1
-
-
70
ns
SDO to Hi-Z state
bit 16/8
thz
-
-
50
ns
SDO to non-Hi-Z
bit 1
tnz
5-
-
ns
RESET pulse width high
250
-
-
µs
Notes: 12. When the CS6403 is in master mode (SSYNC and SCLK outputs), the SCLK duty cycle is 50%.
The period of SCLK is 4/CLKIN.
CS6403
6
DS192PP6




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