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CS6403-IQ Datasheet(PDF) 3 Page - Cirrus Logic

Part No. CS6403-IQ
Description  Echo-Cancelling Codec
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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 3 page
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DAC CHARACTERISTICS (TA = 25 °C; All DVDD, AVDD, and PVDD = 5.0V, Digital Input Levels:
Logic 0 = 0V, Logic 1 = DVDD; Signal test frequency 1kHz, word rate (Fs) = 8kHz, audio signal measurement
bandwidth is 20Hz to 20kHz; Microphone amp gain = 0dB; SPRKOUT outputs connected to 8
Ω load; CLKIN fre-
quency = 8.192MHz; unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
Units
DAC Resolution
12
-
-
bits
DAC step size error
-
-
±0.5
LSB
Instantaneous Dynamic Range (20 Hz - 20 kHz)
IDR
60
72
-
dB
Frequency Response
-0.8
-
+0.6
dB
Programmable Output Level Attenuator Range
(Note 5)
-92.2
-
0
dB
Gain Step Size
-
2.49
-
dB
Gain Drift
(Note 2)
-
150
-
ppm/°C
VREF Reference Output Voltage
-
2.0
-
V
VCM Output Voltage
constant load only, >100k
-1.0
-
V
Offset Error
-
25
50
mV
Full Scale Output Voltage
(SPKROUT pins)
(Note 6)
1.40
1.75
1.93
Vp
Common Mode Output Voltage (SPKROUT pins)
-
1.30
-
V
Total Harmonic Distortion at -0.5dBFS level, SPKROUT(Note 9)
THD
-
-
0.8
%
Output Impedance SPKROUT pins
-
0.4
-
Load Impedance SPKROUT pins
8
-
-
Output Capacitance
-
15
-
pF
Audible Stop Band Attenuation (<20kHz)
68
-
-
dB
Integrated Inaudible Energy
(>20kHz to 100kHz)
(Note 7)
-
-
30
mVrms
Power Supply Rejection
(1kHz)
PSR
40
60
-
dB
Filter Transition Band
0.45
-
0.6
Fs
Group Delay
(Note 8)
-
1
-
ms
Notes:
5. Attenuation settings greater than 92.2 dB will cause a full scale input signal to be completely
attenuated to zero signal level.
6. This is the peak differential output voltage. The peak-to-peak signal level on each output pin is
equal to the peak differential value.
7. Assuming an external 43.2 kHz RC output filter.
8. This group-delay specification is for the DAC only; additional group delay is introduced by the
AGC and high-pass filter that is implemented on the CS6403 in software.
9. Room temperature only.
CS6403
DS192PP6
3




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