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CS6403-IL Datasheet(PDF) 41 Page - Cirrus Logic |
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CS6403-IL Datasheet(HTML) 41 Page - Cirrus Logic |
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41 / 54 page  The far-end input gain is determined by R2, R3, R9, and R10 which are all currently 10k Ω. The resistors are part of a differential amplifier whose gain is (-R2/R3). Note that R2 and R9 should have the same value, as should R3 and R10. Both FE_IN+ and FE_IN- are connected through a 0.1 µF DC blocking capacitor. The far-end output drive capability can be boosted by using the PI, PO+ and PO- pins of the MC145480. PI and PO- are equivalent to the inverting input and output, respectively, of an opamp. PO+ and PO- are differential drivers ca- pable of driving a 150 Ω load. Easy access to PI, PO-, and PO+ is provided through J5, J6, and J7, respectively. See the MC145480 datasheet and Figure 5 for more details. EPLD The EMP7032 EPLD from Altera handles some miscellaneous logic functions on the evaluation board, but is not necessary for operation. It is mainly used to encode the Algorithm Control Switches (SW2-6) to the GPIN2/1/0 pins. It also buffers the DIP switches, and it provides in- verters for the LED bank. The encoding of SW2-6 could have been done without using programmable logic, but the EPLD assures that only legal combinations of buttons are accepted for all modes of operation of the evaluation board. The EPLD provides the function of several buffers, inverters, and AND/OR gates. A Schmitt-trigger inverter U101 is added to provide hardware debouncing of the switches. An added benefit of the EPLD is that it demon- strates effective use of separate ground planes for analog and digital components. Although all of the digital logic in the EPLD is relatively static, the CDB6403 provides a good example of how to split the digital and analog sides of a board. Note that the CS6403 resides completely on the analog side of the board and digital signals cross the break in the ground planes by taking the shortest possible route. RO+ RO- PI PO- PO+ VDD FSR DR BCLKR PDI VAG TI+ TI- TG MU/A VSS FST DT BCLKT MCLK AGND R9 10k 20 C8 X7R 0.1 µF R10 10k 0.1 µF FE_IN- 18 R3 10k C11 X7R FE_IN+ 10k R2 0.1 µF C9 X7R 19 17 UALAW 15 16 AGND SYNCOUT SDI SCLK 14 13 11 12 1 3 2 4 6 5 7 8 10 9 X7R 0.1 µF C5 FE_OUT+ FE_OUT- +5VA SDO CONFIG U3 MC145480 J5 Figure 5. On-board PCM Codec CDB6403 DS192DB3 41 |
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