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CS61304A Datasheet(PDF) 5 Page - Cirrus Logic

Part No. CS61304A
Description  T1/E1 Line Interface
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
(Note 25)
fc
-
8.192000
-
MHz
TCLK Frequency
ftclk
-
2.048
-
MHz
TCLK Pulse Width
(Note 26)
tpwh2
150
-
340
ns
ACLKI Duty Cycle
tpwh3/tpw3
40
-
60
%
ACLKI Frequency
(Note 27)
faclki
-
2.048
-
MHz
RCLK Duty Cycle
(Note 28)
tpwh1/tpw1
45
50
55
%
Rise Time, All Digital Outputs
(Note 29)
tr
-
-
85
ns
Fall Time, All Digital Outputs
(Note 29)
tf
-
-
85
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
RPOS/RNEG Valid Before RCLK Falling
(Note 30)
tsu1
100
194
-
ns
RDATA Valid Before RCLK Falling
(Note 31)
tsu1
100
194
-
ns
RPOS/RNEG Valid Before RCLK Rising
(Note 32)
tsu1
100
194
-
ns
RPOS/RNEG Valid After RCLK Falling
(Note 30)
th1
100
194
-
ns
RDATA Valid After RCLK Falling
(Note 31)
th1
100
194
-
ns
RPOS/RNEG Valid After RCLK Rising
(Note 32)
th1
100
194
-
ns
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
(Note 25)
fc
-
6.176000
-
MHz
TCLK Frequency
ftclk
-
1.544
-
MHz
TCLK Pulse Width
(Note 26)
tpwh2
150
-
500
ns
ACLKI Duty Cycle
tpwh3/tpw3
40
-
60
%
ACLKI Frequency
(Note 27)
faclki
-
1.544
-
MHz
RCLK Duty Cycle
(Note 28)
tpwh1/tpw1
45
50
55
%
Rise Time, All Digital Outputs
(Note 29)
tr
-
-
85
ns
Fall Time, All Digital Outputs
(Note 29)
tf
-
-
85
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
RPOS/RNEG Valid Before RCLK Falling
(Note 30)
tsu1
150
274
-
ns
RDATA Valid Before RCLK Falling
(Note 31)
tsu1
150
274
-
ns
RPOS/RNEG Valid Before RCLK Rising
(Note 32)
tsu1
150
274
-
ns
RPOS/RNEG Valid After RCLK Falling
(Note 30)
th1
150
274
-
ns
RDATA Valid After RCLK Falling
(Note 31)
th1
150
274
-
ns
RPOS/RNEG Valid After RCLK Rising
(Note 32)
th1
150
274
-
ns
Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
26. The transmitted pulse width does not depend on the TCLK duty cycle.
27. ACLKI provided by an external source or TCLK.
28. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
29. At max load of 1.6 mA and 50 pF.
30. Host Mode (CLKE = 1).
31. Extended Hardware Mode.
32. Hardware Mode, or Host Mode (CLKE = 0).
CS61304A
DS156PP2
5
CS61304A
DS156F1
5




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