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CS61304A-IL Datasheet(PDF) 4 Page - Cirrus Logic |
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CS61304A-IL Datasheet(HTML) 4 Page - Cirrus Logic |
4 / 32 page ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Receiver RTIP/RRING Input Impedance - 50k - Ω Sensitivity Below DSX (0dB = 2.4V) -13.6 500 - - - - dB mV Data Decision Threshold T1, DSX-1 (Note 19) T1, DSX-1 (Note 20) T1, FCC Part 68 and E1 (Note 21) 60 53 45 65 65 50 70 77 55 % of peak % of peak % of peak Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 22) 10kHz - 100kHz 2kHz 10Hz and below 0.4 6.0 300 - - - - - - UI UI UI Loss of Signal Threshold (Note 23) 0.25 0.30 0.50 V Jitter Attenuator Jitter Attenuation Curve Corner Frequency (Notes 16, 24) - 3 - Hz Attenuation at 10kHz Jitter Frequency (Notes 16, 24) - 50 - dB Attenuator Input Jitter Tolerance (Notes 16, 24) (Before Onset of FIFO Overflow or Underflow Protection) 138 - - UI Notes: 19. For input amplitude of 1.2 Vpk to 4.14 Vpk. 20. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+. 21. For input amplitude of 1.05 Vpk to 3.3 Vpk. 22. Jitter tolerance increases at lower frequencies. See Figure 11. 23. The analog input squelch circuit shall operate when the input signal amplitude above ground on the RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low. 24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase significantly when more than 138 UI’s are input to the attenuator. See discussion in the text section. CS61304A 4 DS156PP2 CS61304A 4 DS156F1 |
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