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CS61305A-IP1 Datasheet(PDF) 4 Page - Cirrus Logic

Part No. CS61305A-IP1
Description  T1/E1 LINE INTERFACE
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Transmitter Jitter Attenuator
Jitter Attenuation Curve Corner Frequency
(Notes 16, 19)
-
3
-
Hz
Attenuation at 10kHz Jitter Frequency
(Notes 16, 19)
-
50
-
dB
Attenuator Input Jitter Tolerance
(Notes 16, 19)
(Before Onset of FIFO Overflow or Underflow Protection)
138
-
-
UI
Receiver
RTIP/RRING Input Impedance
-
50k
-
Sensitivity Below DSX (0dB = 2.4V)
-13.6
500
-
-
-
-
dB
mV
Data Decision Threshold
T1, DSX-1
(Note 20)
T1, (FCC Part 68) and E1
(Note 21)
53
45
65
50
77
55
% of peak
% of peak
Allowable Consecutive Zeros before LOS
160
175
190
bits
Receiver Input Jitter Tolerance
(Note 22)
10kHz - 100kHz
2kHz
10Hz and below
0.4
6.0
300
-
-
-
-
-
-
UI
UI
UI
Loss of Signal Threshold
-
0.30
-
V
Notes: 19. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 10. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.
20. For input amplitude of 1.2 Vpk to 4.14 Vpk.
21. For input amplitude of 1.05 Vpk to 3.3 Vpk.
22. Jitter tolerance increases at lower frequencies. See Figure 12.
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
(Note 23)
fc
-
8.192000
-
MHz
ACLKI Duty Cycle
tpwh3/tpw3
40
-
60
%
ACLKI Frequency
(Note 24)
faclki
-
2.048
-
MHz
RCLK Cycle Width
(Note 25)
tpw1
tpwh1
tpwl1
310
90
120
488
140
348
620
190
500
ns
ns
ns
Rise Time, All Digital Outputs
(Note 26)
tr
-
-
85
ns
Fall Time, All Digital Outputs
(Note 26)
tf
-
-
85
ns
TCLK Frequency
ftclk
-
2.048
-
MHz
TCLK Pulse Width
(Notes 27, 28)
(Notes 29, 30)
tpwh2
80
150
-
-
-
340
ns
ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
RPOS/RNEG Valid Before RCLK Falling
(Note 27)
tsu1
100
194
-
ns
RDATA Valid Before RCLK Falling
(Note 29)
tsu1
100
194
-
ns
RPOS/RNEG Valid Before RCLK Rising
(Note 28)
tsu1
100
194
-
ns
RPOS/RNEG Valid After RCLK Falling
(Note 27)
th1
100
194
-
ns
RDATA Valid After RCLK Falling
(Note 29)
th1
100
194
-
ns
RPOS/RNEG Valid After RCLK Rising
(Note 28)
th1
100
194
-
ns
CS61305A
4
DS157PP3




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