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CS61310 Datasheet(PDF) 3 Page - Cirrus Logic

Part No. CS61310
Description  T1 INE INTERFACE UNIT
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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CS61310
DS440F1 FEB ‘03
3
3. ARBITRARY WAVEFORM GENERATION ............................................................................ 17
4. PIN DESCRIPTION ................................................................................................................. 20
5. PACKAGE DIMENSIONS ...................................................................................................... 25
6. APPLICATIONS ..................................................................................................................... 27
LIST OF FIGURES
Figure 1.
Signal Rise and Fall Characteristics ............................................................................ 7
Figure 2.
Recovered Clock and Data Switching Characteristics ................................................. 7
Figure 3.
Transmit Clock and Data Switching Characteristics .................................................... 7
Figure 4.
Serial Port Write Timing Diagram ................................................................................ 8
Figure 5.
Serial Port Read Timing Diagram ................................................................................ 8
Figure 6.
Typical Pulse Shape for DS-1 ...................................................................................... 9
Figure 7.
Minimum Input Jitter Tolerance of Receiver .............................................................. 10
Figure 8.
Typical Jitter Transfer Function .................................................................................. 11
Figure 9.
LATN Pulse Width encoding ...................................................................................... 11
Figure 10. Input/Output Timing (showing address 0x10) ............................................................ 13
Figure 11. Phase Definition of Arbitrary Waveforms ................................................................... 17
Figure 12. Example of Summing of Waveforms .......................................................................... 17
Figure 13. Hardware Mode Operation ......................................................................................... 27
Figure 14. Matched Impedence Output Configuration ................................................................ 28
LIST OF TABLES
Table 1.
Pulse Shape Selection and Transformer Requirements ............................................... 9
Table 2.
Data Output/Clock Relationship.................................................................................. 10
Table 3.
Register Map............................................................................................................... 13
Table 4.
Register 16 Decoding ................................................................................................. 15
Table 5.
CS61310 Diagnostic Mode Availability ....................................................................... 18
Table 6.
Transformer Specification ........................................................................................... 19
Table 7.
Recommended Tranformers for the CS61310 ............................................................ 19




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