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CS61581 Datasheet(PDF) 17 Page - Cirrus Logic |
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CS61581 Datasheet(HTML) 17 Page - Cirrus Logic |
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17 / 37 page  CS61581 DS211PP8 17 Figure 12 shows the timing relationships for data transfers when CLKE = 0. When CLKE = 1, data bit D7 is held until the falling edge of the 16th clock cycle. When CLKE = 0, data bit D7 is held valid until the rising edge of the 17th clock cycle. SDO goes high-impedance after CS goes high or at the end of the hold period of data bit D7. SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in applica- tions where the host processor has a bidirectional I/O port. An address/command byte, shown in Figure 12, points to addresses 0x10 through 0x15 (address 0x10 shown), and precedes a data byte. The first bit of the address/command byte determines whether a read or a write is requested. The next six bits con- tain the address. The last bit is ignored. Data to the internal registers is input on the eight clock cycles immediately following the address/command byte. The register bit assignments are shown in Table 3. CS SCLK SDO CLKE = 0 SDI D6 D5 D4 D3 D2 D1 D0 D7 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Address/Command Byte Data Input/Output 0 0 0 1 0 R/W Figure 12. Input/Output Timing (showing address 0x10) 7 6 5 432 1 0 ADDR Control Register 1 LH (CR2.0 = 0) (CR1LH) TAOS LLOOP RLOOP LB02 LB01 CODER TAZ NLOOP LOS 0x10 R/W Control Register 1 SH (CR2.0 = 1) (CR1SH) TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RSVD LOS 0x10 R/W Control Register 2 LH (CR2.0 = 0) (CR2LH) AIS RAMPLSE MATCHZ LOOPDN LOOPUP RPWDN TxHIZ SH/LH 0x11 R/W Control Register 2 SH (CR2.0 = 1) (CR2SH) AIS RAMPLSE MATCHZ RSVD RCODER TCODER TxHIZ SH/LH 0x11 R/W Equalizer Gain (EQGAIN) X X X EQ4 EQ3 EQ2 EQ1 EQ0 0x12 R RAM Address (RAM) MSB - - - - - - LSB 0x13 R/W Control Register 3 (CR3) QRSS- PATH E1_LH RST_ QERR QDET INS_QERR QSYNC TEST QGEN TEST 0x14 R/W Data Pattern Error Count (DPEC) MSB - - - - - - LSB 0x15 R Table 3. Register Map CS61581 DS211F1 17 |
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