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CS61581-IL Datasheet(PDF) 7 Page - Cirrus Logic

Part No. CS61581-IL
Description  T1/E1 Universal Line Interface
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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CS61581
DS211PP8
7
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%;
GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3)
Notes: 19. MCLK provided by an external source or TCLK.
20. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator FIFO limits are reached.
21. At max load of 1.6 mA and 50 pF.
22. Host Mode (CLKE = 1).
23. Host Mode (CLKE = 0)
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0 V ±5%;
GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
TCLK Frequency
ftclk
-1.544
-
MHz
MCLK Frequency
(Note 19)
fmclk
-1.544
-
MHz
RCLK Duty Cycle
(Notes 18, 20) tpwh1/tpw1
50
%
Rise Time, All Digital Outputs
(Note 21)
tr
--
85
ns
Fall Time, All Digital Outputs
(Note 21)
tf
--
85
ns
TPOS/TNEG to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG Hold Time
th2
25
-
-
ns
RPOS/RNEG Valid Before RCLK Falling
(Note 22)
tsu1
150
274
-
ns
RPOS/RNEG Valid Before RCLK Rising
(Note 23)
tsu1
150
274
-
ns
RPOS/RNEG Valid After RCLK Falling
(Note 22)
th1
150
274
-
ns
RPOS/RNEG Valid After RCLK Rising
(Note 23)
th1
150
274
-
ns
Parameter
Symbol
Min
Typ
Max
Units
TCLK Frequency
ftclk
-2.048
-
MHz
MCLK Frequency
(Note 19)
fmclk
-2.048
-
MHz
RCLK Duty Cycle
(Notes 18, 20) tpwh1/tpw1
50
%
Rise Time, All Digital Outputs
(Note 21)
tr
--
85
ns
Fall Time, All Digital Outputs
(Note 21)
tf
--
85
ns
TPOS/TNEG to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG Hold Time
th2
25
-
-
ns
RPOS/RNEG Valid Before RCLK Falling
(Note 22)
tsu1
100
194
-
ns
RPOS/RNEG Valid Before RCLK Rising
(Note 23)
tsu1
100
194
-
ns
RPOS/RNEG Valid After RCLK Falling
(Note 22)
th1
100
194
-
ns
RPOS/RNEG Valid After RCLK Rising
(Note 23)
th1
100
194
-
ns
CS61581
DS211F1
7




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