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CS61581-IL Datasheet(PDF) 10 Page - Cirrus Logic

Part No. CS61581-IL
Description  T1/E1 Universal Line Interface
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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CS61581
10
DS211PP8
2. THEORY OF OPERATION
The CS61581 Universal Line Interface supports T1
and E1 data rates for both short haul and long haul
applications. The transmitter complies with all
standard T1 and E1 applications without changing
transformers. Transmitter power consumption is
minimized using the impedance matching feature,
which eliminates external resistors for standard line
impedances. When configured for long haul opera-
tion, the receiver uses gain and equalization to pro-
vide 40 dB of sensitivity. The receiver reconfigures
for short haul operation, limiting the receive sensi-
tivity and increasing the noise immunity.
2.1
Operating Mode Selection
The CS61581 can be operated in stand-alone hard-
ware interface mode (MODE pin is low), or by a
microcontroller in serial host mode (MODE pin is
high). Additional functionality is available in the
host mode including both short haul and long haul
operational modes. The CS61581 defaults to the
Long Haul configuration (LXT310/318 compati-
ble). The T1 (DSX-1 and Network interface) and
E1 (ITU-T G.703) are selectable via the serial port
by writing to a control register.
Tying TNEG high for more than 16 TCLK cycles
enables the unipolar mode, changing TPOS to
TDATA, RPOS to RDATA, and RNEG to BPV.
When configured for unipolar mode, the MODE
pin can be tied to RCLK enabling the B8ZS encod-
ers and decoders. Coder mode does not support bi-
polar data.
2.2
Master Clocks
The CS61581 requires a reference clock for the re-
ceiver and the jitter attenuator. Either a 1.544 MHz
(or 2.048 MHz) external clock can be input to
MCLK, or a 4X crystal can be connected to the on-
chip oscillator. This frequency reference should be
within 100 ppm of the nominal operating frequen-
cy. Jitter and wander on the reference clock will de-
grade jitter attenuation and receiver jitter tolerance.
If MCLK is provided, the crystal oscillator is ig-
nored.
2.3
Transmitter
The transmitter accepts digital T1 or E1 input data
and drives appropriately shaped AMI (Alternate
Mark Inversion) pulses onto a transmission line
through a transformer. The transmit data (TPOS &
TNEG or TDATA) is sampled on the falling edge
of the input clock, TCLK.
Upon power up, the CS61581 defaults to Long
Haul Mode with low-impedance drive. In this
mode, a 1:2 transformer is required (See Table 1).
The CS61581 will support both T1 and E1 opera-
tion as determined by the master clock frequency.
In host mode, T1 (DSX-1 or Network Interface),
E1 (ITU-T or G.703) or T1 long-haul pulse shapes
may be selected. Long-haul or short-haul operation
is determined by the SH/LH bit (CR2.0). The
SH/LH bit also establishes functionality of Control
Registers 1 and 2.
In the matched impedance configuration, the line
driver internally matches the impedance of the line
load; 75
. or 120 . for E1, and 100 . for T1 using
a 1:1.5 turns ratio transformer. Internal impedance
matching reduces current consumption by about a
factor of two compared to return loss achieved by
external resistors.
The T1 long-haul pulse shapes comply with FCC
Part 68 Option A (0 dB). Option B (-7.5 dB), Op-
tion C (-15 dB) or (-22.5 dB) (see Table 1). If de-
sired, the T1 pre-equalization settings can be
selected for E1 operation as well. In long-haul
mode, pulse shaping and signal level are controlled
by LBO1 and LBO2 pins or register bits.
Custom transmit pulse shapes may be implemented
by writing pulse shape coefficients to the registers.
Custom pulses may be used to correct for pulse
shape degradation or distortion caused by improper
termination, suboptimal interconnect wiring, or
CS61581
10
DS211F1




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