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CS61583 Datasheet(PDF) 10 Page - Cirrus Logic

Part No. CS61583
Description  DUAL T1/E1 LINE INTERFACE
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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tional benefit of the internal impedance matching
is a 50 percent reduction in power consumption
compared to implementing return loss using ex-
ternal resistors that causes the transmitter to
drive the equivalent of two line loads.
The line receiver contains all the necessary clock
and data recovery circuits.
The jitter attenuator meets AT&T 62411 require-
ments when using a 1X or 8X reference clock
supplied by either a crystal oscillator or external
reference at the REFCLK input pin.
AT&T 62411 Customer Premises Application
The AT&T 62411 specification applies to the T1
interface between the customer premises and the
carrier, and must be implemented by the cus-
tomer premises equipment in order to connect to
the AT&T network.
In 62411 applications, the management of jitter
is a very important design consideration. Typi-
cally, the jitter attenuator is placed in the receive
path of the CS61583 to reduce the jitter input to
the system synchronizer. The jitter attenuated re-
covered clock is used as the input to the transmit
clock to implement a loop-timed system. A Stra-
tum 4 (
±32 ppm) quality clock or better should
be input to REFCLK. Note that any jitter present
on the reference clock will not be filtered by the
jitter attenuator.
Asynchronous Multiplexer Application
Asynchronous multiplexers accept multiple
T1/E1 lines (which are asynchronous to each
other), and combine them into a higher speed
transmission rate (e.g. M13 muxes and SONET
muxes). In these systems, the jitter attenuator is
placed in the transmit path of the CS61583 to
remove the gapped clock jitter input by the mul-
tiplexer to TCLK. Because the transmit clock is
jittered, the reference clock to the CS61583 is
provided by an external source operating at 1X
or 8X the data rate. Because T1/E1 framers are
not usually required in asynchronous multiplex-
e rs, the B8 ZS/AMI/HDB3 coders in the
CS61583 are activated to provide data interfaces
on TDATA and RDATA.
Synchronous Application
A typical example of a synchronous application
is a T1 card in a central office switch or a 0/1
digital cross-connect system. These systems
place the jitter attenuator in the receive path to
reduce the jitter presented to the system. A Stra-
tum 3 or better system clock is input to the
CS61583 transmit and reference clocks.
TRANSMITTER
The transmitter accepts data from a T1 or E1
system and outputs pulses of appropriate shape
to the line. The transmit clock (TCLK) and
transmit data (TPOS & TNEG, or TDATA) are
supplied synchronously. Data is sampled on the
falling edge of the TCLK input.
The configuration pins CON[2:0] control trans-
mitted pu lse shapes, transmitter source
impedance, and receiver slicing level as shown in
Table 1. Typical output pulses are shown in Figures
6 and 7. These pulse shapes are fully pre-defined
by circuitry in the CS61583, and are fully compli-
ant with appropriate standards when used with our
application guidelines in standard installations.
Both channels must be operated at the same line rate
(both T1 or both E1).
Note that the pulse width for Part 68 Option A
(324 ns) is narrower than the optimal pulse
width for DSX-1 (350 ns). The CS61583 auto-
matically adjusts the pulse width based on the
configuration selection.
The transmitter impedance changes with the line
length options in order to match the load imped-
ance (75
Ω for E1 coax, 100Ω for T1, 120Ω for
E1 shielded twisted pair), providing a minimum
of 14 dB return loss for T1 and E1 frequencies
CS61583
10
DS172PP5




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