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CS61584A-IL3 Datasheet(PDF) 18 Page - Cirrus Logic |
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CS61584A-IL3 Datasheet(HTML) 18 Page - Cirrus Logic |
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18 / 54 page  CS61584A 18 DS261PP5 DS261PP5 The transmitter impedance changes with the line length options in order to match the load imped- ance (75 Ω for E1 coax, 100 Ω for T1, 120 Ω for E1 shielded twisted pair), providing a minimum of 14 dB return loss for T1 and E1 frequencies during the transmission of both marks and spaces. This improves signal quality by minimizing reflections from the transmitter. Impedance matching also re- duces load power consumption by a factor of two when compared to the return loss achieved by using external resistors. The CS61584A driver will automatically detect an inactive TLCK (i.e., no data clocked to the driver) or REFCLK input. When either of these conditions are detected the driver is forced to the tristate (high- impedance) condition. If the jitter attenuator is in the transmit path, the driver will tristate after 170 to 182 TCLK clock cycles. If the attenuator is not in the transmit path, the driver will tristate after 4 to 12 TCLK clock cycles. During Host mode opera- tion, the CLKLOST bit in the Status register goes high to indicate when the driver is tristated due to the absence of TCLK or REFCLK. The driver exits the tristate condition when four clock cycles are in- put to TCLK. On power-up or reset, the driver is tristated until REFCLK is present and four clock cycles are input to TCLK. In Host mode the driver will have to be taken out of the tristate condition by writing the CON[3:0]. The driver is not forced to the tristate condition during remote loopback if TCLK is absent. When the transmit configuration established by CON[3:0], TAOS, or LLOOP changes state, the transmitter stabilizes within 22 TCLK bit periods. The transmitter takes longer to stabilize when RLOOP1 or RLOOP2 is selected because the tim- ing circuitry must adjust to the new frequency from RCLK. When the transmitter transformer secondaries are shorted through a 0.5 Ω resistor, the transmitter will output a maximum of 50 mA-rms, as required by the European specification BS6450. This spec is met for 5.0 V operation only. 4. RECEIVER The input signal is connected to the receiver through a step down transformer (1.15:1 for 5 V and 2:1 for 3.3 V). Data and clock are extracted from the T1/E1 signal input to the line interface and to the system. The signal is detected differentially across the receive transformer and can be recov- ered over the entire range of short haul cable lengths. The transmit and receive transformer spec- ifications are identical and are presented in the Ap- plications section. As shown in Table 1, the receiver slicing level is set at 65% for DS1/DSX-1 short-haul and at 50% for all other applications. The clock recovery circuit is a second-order phase locked loop that can tolerate up to 0.4 UI of jitter from 10 kHz to 100 kHz without generating errors (Figure 13). The clock and data recovery circuit is tolerant of long strings of consecutive zeros and will successfully recover a 1-in-175 jitter-free line input signal. Recovered data at RPOS and RNEG (or RDATA) is stable and may be sampled using the recovered clock RCLK. During Hardware mode operation, 10 1k 10k 1 100 100k 700 .1 1 10 100 .4 28 300 300 PEAK-TO-PEAK JITTER (unit intervals) JITTER FREQUENCY (Hz) CS61584A Performance 138 AT&T 62411 (1990 Version) Figure 16. Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and jitter Attenuator) CS61584A 18 DS261F1 |
Similar Part No. - CS61584A-IL3 |
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Similar Description - CS61584A-IL3 |
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