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CS61584A-IL3 Datasheet(PDF) 42 Page - Cirrus Logic |
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CS61584A-IL3 Datasheet(HTML) 42 Page - Cirrus Logic |
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42 / 54 page  CS61584A 42 DS261PP5 DS261PP5 REFCLK - External Reference Clock Input (PLCC pin 36; TQFP pin 26) Input reference clock for the receive and jitter attenuator circuits. When 1XCLK is high, REFCLK must be a 1X clock (i.e., 1.544 MHz ±100 ppm for T1 applications or 2.048 MHz ±100 ppm for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e., 12.352 MHz ±100 ppm for T1 applications or 16.384 MHz ±100 ppm for E1 applications). The REFCLK input also determines the transmission rate when TAOS is asserted. XTALOUT - Crystal Oscillator Output (PLCC pin 37; TQFP pin 27) A quartz crystal with a resonant frequency of 12.352 MHz for T1 applications or 16.384 MHz for E1 applications may be connected across the XTALOUT and REFCLK pins instead of using a CMOS compatible clock source. The 1XCLK pin must be set low to select 8X clock operation. This pin must remain unconnected if a quartz crystal is not used. Control ATTEN0, ATTEN1 - Attenuator Select [Hardware Mode] (PLCC pins 25, 8; TQFP pins 16, 64) Selects the jitter attenuator path and -3 dB knee point for both channels (transmit/receive/neither). See Table 3. CLKE - Clock Edge [Hardware mode] (PLCC pin 44; TQFP pin 33) Controls the polarity of the recovered clock RCLK. When CLKE is high, RPOS and RNEG (or RDATA) are valid on the falling edge of RCLK. When CLKE is low, RPOS and RNEG (or RDATA) are valid on the rising edge of RCLK. CON01, CON11 - Configuration Selection for Channel 1 [Hardware Mode] CON21, CON31 - (PLCC pins 2, 65, 63, 61; TQFP pins 58, 53, 51, 49) CON02, CON12 - Configuration Selection for Channel 2 [Hardware Mode] CON22, CON32 - (PLCC pins 66, 64, 62, 52; TQFP pins 54, 52, 50, 41) These pins configure the transmitter (pulse shape, pulse width, pulse amplitude, and driver impedance), receiver (slicing level), coder (HDB3 vs B8ZS), and driver tristate. The CONx1 pins control channel 1 and the CONx2 pins control channel 2. Both channels must be configured to operate at the same data rate on the line interface (both T1 or both E1). The arbitrary waveform options are not available during Hardware mode operation. See Table 1. LLOOP - Local Loopback [Hardware Mode] (PLCC pin 5; TQFP pin 61) A local loopback #2 of both channels is enabled when LLOOP is high. Selecting LLOOP causes the TCLK, TPOS/TNEG (TDATA) inputs to be looped back through the transmitter, receiver and jitter attenuator (if enabled) to the RCLK, RPOS/RNEG (RDATA) outputs. The data at TPOS/TNEG (TDATA) continues to be transmitted to the line interface unless overridden by a TAOS request. The input on RTIP and RRING is ignored. When the RLOOP and TAOS pins are both high, the TCLK, TPOS/TNEG (TDATA) inputs are looped back (local loopback #1) through the jitter attenuator (if enabled) to the RCLK, RPOS/RNEG (RDATA) outputs for the selected channel. The data at TPOS/TNEG (TDATA) is also overridden with an all-ones pattern (TAOS). The receive input at RTIP and RRING is ignored. MODE - Mode Select (PLCC pin 31; TQFP pin 21) Hardware mode operation is selected when MODE is low, enabling the device to be configured and monitored using control pins. Host mode operation is selected when MODE is high, enabling the device to be configured and monitored over a microprocessor interface using the internal register set. CS61584A 42 DS261F1 |
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