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CS61584A-IQ5Z Datasheet(PDF) 34 Page - Cirrus Logic |
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CS61584A-IQ5Z Datasheet(HTML) 34 Page - Cirrus Logic |
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34 / 54 page  CS61584A 34 DS261PP5 DS261PP5 10.5 Run-Test/Idle State This is a controller state between scan operations. Once in this state, the controller remains in the state as long as J-TMS is held low. The instruction reg- ister and all test data registers retain their previous state. When J-TMS is high and a rising edge is ap- plied to J-TCK, the controller moves to the Select- DR state. 10.6 Select-DR-Scan State This is a temporary controller state and the instruc- tion does not change in this state. The test data reg- ister selected by the current instruction retains its previous state. If J-TMS is held low and a rising edge is applied to J-TCK when in this state, the controller moves into the Capture-DR state and a scan sequence for the selected test data register is initiated. If J-TMS is held high and a rising edge applied to J-TCK, the controller moves to the Se- lect-IR-Scan state. 10.7 Capture-DR State In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-DR state if J-TMS is high or the Shift-DR state if J-TMS is low. 10.8 Shift-DR State In this controller state, the test data register con- nected between J-TDI and J-TDO as a result of the current instruction shifts data on stage toward its serial output on each rising edge of J-TCK. The in- struction does not change in this state. When the TAP controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1- DR state if J-TMS is high or remains in the Shift- DR state if J-TMS is low. 10.9 Exit1-DR State This is a temporary state. While in this state, if J- TMS is held high, a rising edge applied to J-TCK causes the controller to enter the Update-DR state, which terminates the scanning process. If J-TMS is held low and a rising edge is applied to J-TCK, the controller enters the Pause-DR state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. Test-Logic-Reset Run-Test/Idle Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR 1 0 0 1 1 0 1 0 1 1 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 Figure 24. TAP Controller State Diagram CS61584A 34 DS261F1 |
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