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EP9315 Datasheet(PDF) 11 Page - Cirrus Logic

Part # EP9315
Description  Enhanced Universal Platform System-on-Chip Processor
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

EP9315 Datasheet(HTML) 11 Page - Cirrus Logic

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©Copyright 2005 Cirrus Logic (All Rights Reserved)
11
EP9315
Enhanced Universal Platform SOC Processor
Note:
Port F defaults as PCMCIA pins. Port F must be
configured by software to be used as GPIO.
Reset and Power Management
The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.
Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.
The processor clock is dynamically adjustable from 0 to
200 MHz (184 MHz for industrial conditions).
Hardware Debug Interface
The JTAG interface allows use of ARM’s Multi-ICE or
other in-circuit emulators.
Note:
The JTAG interface does not support boundary scan.
Internal Boot ROM
The Internal 16-kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP93xx User’s
Manual for operational details
12-channel DMA Controller
The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral
access.
Two
of
these
are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.
The request bus is a collection of requests, Serial Audio,
and
UARTs.
Each
DMA
channel
can
be
used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can
be
independently
programmed
to
increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.
PCMCIA Interface
The EP9315 has a single PCMCIA port which can be
used to access either 8 or 16-bit devices.
Table P. General Purpose Input/Output Pin Assignment
Pin Mnemonic
Pin Name - Description
EGPIO[15:0]
Expanded General Purpose Input / Output
Pins with Interrupts
FGPIO[7:0]
Expanded General Purpose Input / Output
Pins with Interrupts
Table Q. Reset and Power Management Pin Assignments
Pin Mnemonic
Pin Name - Description
PRSTn
Power On Reset
RSTOn
User Reset In/Out – Open Drain –
Preserves Real Time Clock value
Table R. Hardware Debug Interface
Pin Mnemonic
Pin Name - Description
TCK
JTAG Clock
TDI
JTAG Data In
TDO
JTAG Data Out
TMS
JTAG Test Mode Select
TRSTn
JTAG Port Reset
Table S. PCMCIA Interface
Pin Mnemonic
Pin Name - Description
VS1
Voltage sense
VS2
Voltage sense
MCD1
Card detect
MCD2
Card detect
MCBVD1
Voltage detection / status change
MCBVD2
Voltage detection
MCDIR
Data transceiver direction control
MCDAENn
Data bus transceiver enable
MCADENn
Address bus transceiver enable
MCREGn
Memory card register
MCEHn
Memory card high byte select
MCELn
Memory card low byte select
IORDn
I/O card read
IOWRn
I/O card write
MCRDn
Memory card read
MCWRn
Memory card write
READY
Ready / interrupt
WP
Write protect
MCWAITn
Wait Input
MCRESETn
Card reset


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