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MPC92433 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MPC92433 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 20 page Advanced Clock Drivers Devices 10 Freescale Semiconductor MPC92433 synthesizer, which have an immediate effect on the PLL frequency. Figure 3. I2C Mode Register Set Figure 3 illustrates the synthesizer register set. PLL_L and PLL_H store a PLL configuration and are fully accessible (Read/Write) by the I2C bus. CMD (Write only) accepts commands (LOAD, GET, INC, DEC) to update registers and for direct PLL frequency changes. Set the synthesizer frequency: 1) Write the PLL_L and PLL_H registers with a new configuration (see Table 13 and Table 14 for register maps) 2) Write the LOAD command to update the PLL dividers by the current PLL_L, PLL_H content. Read the synthesizer frequency: 1) Write the GET commands to update the PLL_L, PLL_H registers by the PLL divider setting 2) Read the PLL_L, PLL_H registers through I2C Change the synthesizer frequency in small steps: 1) Write the INC or DEC command to change the PLL frequency immediately. Repeat at any time if desired. LOAD and GET are inverse command to each other. LOAD updates the PLL dividers and GET updates the configuration registers. A fast and convenient way to change the PLL frequency is to use the INC (increment M) and DEC (decrement M) commands of the synthesizer. INC (DEC) directly increments (decrements) the PLL-feedback divider M and immediately changes the PLL frequency by the smallest step G (see Table 7 for the frequency granularity G). The INC and DEC commands are designed for multiple and rapid PLL frequency changes as required in frequency margining applications. INC and DEC do not require the user to update the PLL dividers by the LOAD command, INC and DEC do not update the PLL_L and PLL_H registers either (use LOAD for an initial PLL divider setting and, if desired, use GET to read the PLL configuration). Note that the synthesizer does not check any boundary conditions such as the VCO frequency range. Applying the INC and DEC commands could result in invalid VCO frequencies (VCO frequency beyond lock range). Register Maps Register 0x00 (PLL_L) contains the least significant bits of the PLL feedback divider M. Register content: M[7:0] PLL feedback-divider M, bits 7–0 Register 0x01 (PLL_H) contains the two most significant bits of the PLL feedback divider M, four bits to control the PLL post-dividers N and the PLL pre-divider P. The bit 0 in PLL_H register indicates the lock condition of the PLL and is set by the synthesizer automatically. The LOCK state is a copy of the PLL lock signal output (LOCK). A write-access to LOCK has no effect. Register content: M[9:8] PLL feedback-divider M, bits 9–8 NA[2:0] PLL post-divider NA, see Table 9 NB PLL post-divider NB, see Table 9 P PLL pre-divider P, see Table 8 LOCK Copy of LOCK output signal (read-only) Note that the LOAD command is required to update the PLL dividers by the content of both PLL_L and PLL_H registers. Register 0xF0 (CMD) is a write-only command register. The purpose of CMD is to provide a fast way to increase or decrease the PLL frequency and to update the registers. The register accepts four commands, INC (increment M), DEC (decrement M), LOAD and GET (update registers). It is recommended to write the INC, DEC commands only after a valid PLL configuration is achieved. INC and DEC only affect the M-divider of the PLL (PLL feedback). Applying INC and DEC commands can result in a PLL configuration beyond the specified lock range and the PLL may lose lock. The MPC92433 does not verify the validity of any commands such as LOAD, INC, and DEC. The INC and DEC commands change the PLL feedback divider without updating PLL_L and PLL_H. Configuration Latches I2C Registers I2C Access Synthesizer – PLL PN M LOAD/GET PLL_L (R/W) 0x00 PLL_H (R/W) 0x01 CMD (W) 0xF0 Table 12. Configuration Registers Address Name Content Access 0x00 PLL_L Least significant 8 bits of M R/W 0x01 PLL_H Most significant 2 bits of M, P, NA, NB, and lock state R/W 0xF0 CMD Command register (write only) W only Table 13. PLL_L (0x00, R/W) Register Bit 7654321 0 Name M7 M6 M5 M4 M3 M2 M1 M0 Table 14. PLL_H (0x01, R/W) Register Bit 76 5 432 1 0 Name M9 M8 NA2 NA1 NA0 NB P LOCK |
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Similar Description - MPC92433 |
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