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ISL6308CRZ-T Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6308CRZ-T Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 27 page 10 FN9208.2 October 19, 2005 currents from a three-phase converter combining to reduce the total input ripple current. The converter depicted in Figure 2 delivers 1.5V to a 36A load from a 12V input. The RMS input capacitor current is 6.1A. Compare this to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has a 13.3A RMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current capacity as the equivalent three- phase converter. Figures 24, 25 and 26 in the section entitled Input Capacitor Selection can be used to determine the input capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6308 is three. One switching cycle is defined as the time between the internal PWM1 pulse termination signals. The pulse termination signal is the internally generated clock signal that triggers the falling edge of PWM1. The cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. Each cycle begins when the clock signal commands PWM1 to go low. The PWM1 transition signals the internal channel 1 MOSFET driver to turn off the channel 1 upper MOSFET and turn on the channel 1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse terminates 1/3 of a cycle after the PWM1 pulse. The PWM3 pulse terminates 1/3 of a cycle after PWM2. If PVCC3 is left open or connected to ground, two channel operation is selected and the PWM2 pulse terminates 1/2 of a cycle after the PWM1 pulse terminates. If both PVCC3 and PVCC2 are left open or connected to ground, single channel operation is selected. The 2PH and 3PH inputs can also be used to accomplish this function. Once a PWM pulse transitions low, it is held low for a minimum of 1/3 cycle. This forced off time is required to ensure an accurate current sample. Current sensing is described in the next section. After the forced off time expires, the PWM output is enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the current correction signal relative to the sawtooth ramp as illustrated in Figure 3. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output transitions high. The internal MOSFET driver detects the change in state of the PWM signal and turns off the synchronous MOSFET and turns on the upper MOSFET. The PWM signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the PWM signal low. Channel Current Balance One important benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this the designer avoids the complexity of driving parallel MOSFETs and the expense of using expensive heat sinks and exotic magnetic materials. In order to realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to carry about the same amount of current at any load level. To achieve this, the currents through each channel must be sampled every switching cycle. The sampled currents, In, from each active channel are summed together and divided by the number of active channels. The resulting cycle average current, IAVG, provides a measure of the total load current demand on the converter during each switching cycle. Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current- balance method is illustrated in Figure 3, with error correction for channel 1 represented. In the figure, the cycle average current, IAVG, is compared with the channel 1 sample, I1, to create an error signal IER. The filtered error signal modifies the pulse width commanded by VCOMP to correct any unbalance and force IER toward zero. The same method for error signal correction is applied to each active channel. FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT- CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER CHANNEL 1 INPUT CURRENT CHANNEL 2 INPUT CURRENT CHANNEL 3 INPUT CURRENT INPUT-CAPACITOR CURRENT ISL6308 |
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