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ISL6421AER Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL6421AER Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 12 page 6 FN9167.2 February 11, 2005 Functional Description The ISL6421A is a single output voltage regulator controlled by an I2C bus, making it an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for a low noise block (LNB) are available simultaneously in any output configuration. The device utilizes a built-in DC/DC step-converter which, from a single supply source ranging from 8V to 14V, generates the voltage that enables the linear post-regulator to work with a minimum of dissipated power. An undervoltage lockout circuit disables the circuit when VCC drops below a fixed threshold (7.5V typ). DiSEqC Encoding The internal oscillator is factory-trimmed to provide a tone of 22kHz in accordance with DiSeqC standards. No further adjustment is required. The 22kHz oscillator can be controlled either by the I2C interface (ENT bit) or by a dedicated pin (DSQIN) that allows immediate DiSEqC data encoding for the LNB. All the functions of this IC are controlled via the I2C bus by writing to the system registers (SR). The same registers can be read back, and two bits will report the diagnostic status. The internal oscillator operates the converters at ten times the tone frequency. The device offers full I2C compatible functionality, 3.3V or 5V, and up to 400kHz operation. If the Tone Enable (ENT) bit is set LOW through I2C, then the DSQIN terminal activates the internal tone signal, modulating the dc output with a 0.3V, 22kHz, symmetrical waveform. The presence of this signal usually gives the LNB information about the band to be received. Burst coding of the 22kHz tone can be accomplished due to the fast response of the DSQIN input and rapid tone response. This allows implementation of the DiSEqC (EUTELSAT) protocols. When the ENT bit is set HIGH, a continuous 22kHz tone is generated regardless of the DSQIN pin logic status. The ENT bit must be set LOW when the DSQIN pin is used for DiSEqC encoding. Linear Regulator The output linear regulator will sink and source current. This feature allows full modulation capability into capacitive loads as high as 0.25 µF. In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. When the device is put in the shutdown mode (EN = LOW), the PWM power block is disabled. When the regulator block is active (EN = HIGH), the output can be logic controlled to be 13V or 18V (typical) by means of the VSEL bit (Voltage Select) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typical) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (LLC bit HIGH). Output Timing The programmed output voltage rise and fall times can be set by an external capacitor. The output rise and fall times will be approximately 3400 times the TCAP value. For the recommended range of 0.47 µF to 2.2µF, the rise and fall time would be 1.6ms to 7.6ms. Using a 0.47 µF capacitor insures the PWM stays below its overcurrent threshold when charging a 120 µF VSW filter cap during the worst case 13V to 19V transition. A typical value of 1.0 µF is recommended. This feature affects the programmed voltage rise and fall times. Current Limiting The current limiting block can operate either statically (simple current clamp) or dynamically. The threshold is between 500mA and 625mA. When the DCL (Dynamic Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically. That is, as soon as an overload is detected, the output is shut down for a time TOFF, typically VCC Main power supply to the chip. GATE This is the device output of the PWM. This high current driver output is capable of driving the gate of a power FET. This output is actively held low when Vcc is below the UVLO threshold. VOUT Output voltage for the LNB. ADDRESS Address pin to select two different addresses per voltage level at this pin. COMP Error amp output used for compensation. FB Feedback pin for the PWM. CPVOUT, CPSWIN, CPSWOUT Charge pump connections. SEL18V When connected HIGH, this pin will change the output of the PWM to 18V. Only available on the QFN package option. Functional Pin Description (Continued) SYMBOL FUNCTION ISL6421A |
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