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ISL6425ER Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6425ER Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 12 page 8 FN9176.1 February 8, 2005 Output Timing The programmed output voltage rise and fall times can be set by an external capacitor. The output rise and fall times will be approximately 3400 times the TCAP value. For the recommended range of 0.47 µF to 2.2µF, the rise and fall time would be 1.6ms to 7.6ms. Using a 0.47 µF capacitor insures the PWM stays below its overcurrent threshold when charging a 120 µF VSW filter cap during the worst case 13V to 19V transition. A typical value of 1.0 µF is recommended. This feature affects the programmed voltage rise and fall times. Current Limiting (Only one ISEL option needed) The current limiting block can operate either statically (simple current clamp) or dynamically. The lower threshold is between 425mA and 550mA (ISEL = L), while the higher threshold is between 775mA and 950mA (ISEL = H). When the DCL (Dynamic Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically. That is, as soon as an overload is detected, the output is shutdown for a time tOFF, typically 900ms. Simultaneously the overload flag (OLF) bit of the system register is set to HIGH. After this time has elapsed, the output is resumed for a time Ton = 20ms. During Ton, the device output will be current limited to between 575mA and 950mA. At the end of Ton, if the overload is still detected, the protection circuit will cycle again through Toff and Ton. At the end of a full Ton during which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical Ton+Toff time is 920ms as determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up, when the dynamic protection is chosen. This can be solved by initiating a power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current limit threshold at the CS pin reaches 0.45V typ and returns LOW when the overload condition is cleared. The OLF bit will be LOW at the end of initial power-on soft-start. Thermal Resistance This IC is protected against overheating. When the junction temperature exceeds 150°C (typical), the step-up converter and the linear regulator are shut off and the overtemp flag (OTF) bit of the SR is set HIGH. Normal operation is resumed and the OTF bit is reset LOW, when the junction is cooled down to 130°C (typical). External Output Voltage Selection The output voltage can be selected by the I2C bus. Additionally, the QFN package offers a pin (SEL18V) for independent 13V/18V output voltage selection. When using this pin, the I2C bits should be initialized to 13V status. I2C Bus Interface for ISL6425 (Refer to Philips I2C Specification, Rev. 2.1) Data transmission from main microprocessor to the ISL6425 and vice versa takes place through the 2 wire I2C bus interfaces, consisting of the two lines SDA and SCL. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stage of ISL6425 will have an open drain/open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100kbits/s in the standard-mode or up to 400kbits/s in the fast-mode. The level of logic “0” and logic “1” is dependent of associated value of Vdd as per electrical specification table. One clock pulse is generated for each data bit transferred. Data Validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. (Refer to Figure 1.) START and STOP Conditions As shown in the Figure 2, START condition is a HIGH to LOW transition of the SDA line, while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line, while SCL is HIGH. A STOP condition must be sent before each START condition. TABLE 1. I2C BITS SEL18V O/P VOLTAGE 13V Low 13V 13V High 18V SDA SCL DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED FIGURE 1. DATA VALIDITY ISL6425 |
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