8

The remaining outputs are also programmed to follow the

SS pin voltage. The PGOOD signal toggles ‘high’ when all

output voltage levels have exceeded their undervoltage

SELECT is held ‘high’. The AGP bus voltage is controlled in

the same manner as the other linear regulators during the

soft-start sequence. Once the soft-start sequence is

complete (t4), the gate of the external pass device is fully

Soft-Start Interval section under Applications Guidelines for

a procedure to determine the soft-start interval.

Fault Protection

All four outputs are monitored and protected against extreme

overload. A sustained overload on any output or an

and drives the FAULT/RT pin to VCC.

Figure 3 shows a simplified schematic of the fault logic. An

overvoltage detected on VSEN1 immediately sets the fault

latch. A sequence of three overcurrent fault signals also sets

the fault latch. The overcurrent latch is set dependent upon

the states of the overcurrent (OC), linear undervoltage (LUV)

and the soft-start signals. A window comparator monitors the

signal). An undervoltage on either linear output (VSEN2,

VSEN3, or VSEN4) is ignored until after the soft-start interval

increase without fault at start-up. Cycling the bias input

counter and the fault latch.

Overvoltage Protection

During operation, a short on the upper MOSFET of the PWM

exceeds the overvoltage threshold of 115% of DACOUT, the

overvoltage comparator trips to set the fault latch and turns

fault latch raises the FAULT/RT pin to VCC.

A separate overvoltage circuit provides protection during the

initial application of power. For voltages on the VCC pin

below the POR (and above ~4V), the output level is

monitored for voltages above 1.3V. Should VSEN1 exceed

this level, the lower MOSFET, Q2 is driven on.

Overcurrent Protection

All outputs are protected against excessive overcurrents.

The PWM controller uses the upper MOSFET’s

against shorted output. All linear controllers monitor their

respective VSEN pins for undervoltage events to protect

against excessive currents.

Figure 4 illustrates the overcurrent protection with an

overload on OUT1. The overload is applied at T0 and the

the OVERCURRENT comparator trips when the voltage

ROCSET. This inhibits all outputs, discharges the soft-start

cycle with the error amplifiers clamped by soft-start. With

OUT1 still overloaded, the inductor current increases to trip

the overcurrent comparator. Again, this inhibits all outputs,

but the soft-start voltage continues increasing to 4V before

discharging. The counter increments to 2. The soft-start

cycle repeats at t3 and trips the overcurrent comparator. The

SS pin voltage increases to 4V at t4 and the counter

increments to 3. This sets the fault latch to disable the

converter. The fault is reported on the FAULT/RT pin.

The linear controllers operate in the same way as the PWM

in response to overcurrent faults. The differentiating factor

FIGURE 2. SOFT-START INTERVAL

0V

0V

0V

TIME

PGOOD

SOFT-START

(1V/DIV)

OUTPUT

(0.5V/DIV)

VOLTAGES

T1

T2

T3

T0

T4

FAULT

LATCH

S

R

Q

POR

COUNTER

OC1

OV

LUV

+

-

+

-

0.15V

4V

SS

VCC

FAULT

R

FIGURE 3. FAULT LOGIC - SIMPLIFIED SCHEMATIC

UP

OVER-

CURRENT

LATCH

INHIBIT

S

R

Q

ISL6440A