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ISL6522BCB Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6522BCB Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 15 page  9 Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, CSS close to the SS pin because the internal current source is only 10 µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (error amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC. Modulator Break Frequency Equations The compensation network consists of the error amplifier (internal to the ISL6522B) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees . The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use these guidelines for locating the poles and zeros of the compensation network: Compensation Break Frequency Equations 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES +12V ISL6522B SS GND VCC BOOT D1 LO CO VOUT Q1 Q2 PHASE +VIN CBOOT CVCC CSS FIGURE 7. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN VOUT OSC REFERENCE LO CO ESR VIN ∆VOSC ERROR AMP PWM DRIVER (PARASITIC) - REF R1 R3 R2 C3 C2 C1 COMP VOUT FB ZFB ISL6522B ZIN COMPARATOR DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN ZFB + FLC 1 2 π LO CO • • --------------------------------------- = FESR 1 2 π ESR CO • () • --------------------------------------------- = FZ1 1 2 π R • 2C1 • ---------------------------------- = FZ2 1 2 π R1 R3 + () C3 • • ------------------------------------------------------ = FP1 1 2 π R2 • C1 C2 • C1 C2 + ---------------------- • ------------------------------------------------------- = FP2 = 1 2 π R3 C3 • • ---------------------------------- ISL6522B |
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