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ISL6534CR Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6534CR Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 26 page  9 FN9134.1 VCC This power pin supplies bias to the control functions. It can be connected to a nominal 5V (±10%) supply, or it can function as a shunt regulator (nominal 5.8V), with an external pull-up resistor (nominally 150 Ω to 12V). GND This pin is the signal ground for the IC. The metal thermal pad under both packages is connected to the GND potential (through the IC substrate; the pad does NOT substitute for the GND pin connection). But the GND pin and the metal pad should be connected together on the board, and tied to a good GND plane (both for electrical and thermal conduction). Note that the thermal pad on both packages limits metal interconnect traces underneath the package. VCC12 (QFN: VCC12_1, VCC12_2) This power pin (nominal 12V) supplies the output gate drivers, as well as some other control functions. The QFN package has two power pins; one for each switcher. They are electrically connected internally, but allow for separate decoupling caps to better isolate the switching noise, if necessary. Even if they share one capacitor, they should both be connected externally, for lower resistance. PGND (QFN: PGND_1, PGND_2) This pin is the Power GND for the gate drive circuits. It is not directly tied to GND inside the IC; it should be tied to GND on the board. The QFN package has two Power GNDs; one local to each switcher; both should be connected externally to the GND plane on the board. SS1/EN1, SS2/EN2, SS3/EN3 These analog input pins have two functions. A 30µA current source charges an external capacitor (to GND), to provide a soft-start timing ramp; their respective Output voltage will follow the ramp voltage as it powers up. The 2nd function is Enable; when the input is left open (with the soft-start cap), the respective output will be Enabled after the ramp reaches the 1V level. If the input is pulled to a low logic level, the output will be disabled. SS2/EN2 also has a special mode function; see Table 1. Tying it to VCC (5V) selects the DDR mode (where both OUT1 and OUT2 share the SS1 ramp); otherwise it will be in the Independent mode. COMP1, COMP2 These analog output pins are used to externally compensate the error amplifiers for their respective regulators. Pin Description 24-PIN TSSOP TOP VIEW 32 LD 5x5 QFN TOP VIEW NOTES: 6. BOOT2 and UGATE2 are different order in QFN. 7. NC is No Connect FB1 COMP1 COMP2 FB2 REFIN SS2/EN2 BOOT2 VCC12 FS_SYNC LGATE2 PGND SS3/EN3 PGOOD SS1/EN1 LGATE1 VREF REFOUT UGATE2 GND DRIVE3 FB3 UGATE1 BOOT1 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND BOTTOM SIDE PAD REFIN NC REFOUT NC PGND_2 LGATE2 PGND_1 UGATE1 LGATE1 VREF DRIVE3 SS2/EN2 SS1/EN1 SS3/EN3 VCC12_1 VCC12_2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 1314 1516 GND BOTTOM SIDE PAD ISL6534 |
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