11

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the

output voltage setting. Be sure to check both of these

equations at the minimum and maximum output levels for

the worst case response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place

the small ceramic capacitors physically close to the

MOSFETs and between the drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

For a through-hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge-current at power-up. The TPS series available from

AVX, and the 593D series from Sprague are both surge

current tested.

MOSFET Selection/Considerations

The ISL6522B requires two N-Channel power MOSFETs.

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

components; conduction loss and switching loss. The

conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor. The switching losses seen when

sourcing current will be different from the switching losses seen

when sinking current. When sourcing current, the upper

MOSFET realizes most of the switching losses. The lower

switch realizes most of the switching losses when the converter

is sinking current (see the equations below).

These equations assume linear voltage-current transitions

and do not adequately model power loss due the reverse-

recovery of the upper and lower MOSFET’s body diode. The

gate-charge losses are dissipated by the ISL6522B and do

not heat the MOSFETs. However, large gate-charge

upper MOSFET switching losses. Ensure that both

MOSFETs are within their maximum junction temperature at

high ambient temperature by calculating the temperature

rise according to package thermal-resistance specifications.

A separate heatsink may be necessary depending upon

MOSFET power, package type, ambient temperature and air

flow.

Standard-gate MOSFETs are normally recommended for

use with the ISL6522B. However, logic-level gate MOSFETs

can be used under special circumstances. The input voltage,

upper gate drive level, and the MOSFETs absolute gate-to-

source voltage rating determine whether logic-level

MOSFETs are appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by

develops a floating supply voltage referenced to the PHASE

turns on. A logic-level MOSFET can only be used for Q1 if

the MOSFETs absolute gate-to-source voltage rating

logic-level MOSFET can be used if its absolute gate-to-

source voltage rating exceeds the maximum voltage applied

to PVCC.

×

-------------------------------

=

×

–

--------------------------------

=

Losses while Sourcing Current

Losses while Sinking Current

P

LOWER

Io

2

r

DS ON

()

×

1D

–

()

×

1

2

--- Io

⋅

V

IN

×

t

SW

F

S

×

×

+

=

Io

2

r

DS ON

()

×

D

×

1

2

--- Io

⋅

V

IN

×

t

SW

F

S

×

×

+

=

ISL6522B