 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
X4C105 Datasheet(PDF) 8 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
X4C105 Datasheet(HTML) 8 Page - Intersil Corporation |
|
|
8 / 19 page  8 FN8124.0 March 18, 2005 Figure 9. Current Address Read Sequence Figure 10. Random Address Read Sequence The device offers a similar operation, called “Set Cur- rent Address,” where the device ends the transmission and issues a stop instead of the second start, shown in Figure 10. The device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next current address read operation will then read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicat- ing it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory con- tents to be serially read during one operation. At the end of the address space the counter “rolls over” to address 0000H and the device continues to output data for each acknowledge received. Refer to Figure 11 for the acknowledge and data transfer sequence. SERIAL DEVICE ADDRESSING Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several parts: – a device type identifier that is always ‘1010’. – two bits that provide the device select bits. – one bit that becomes the MSB of the address. – one bit of the slave command byte is a R/W bit. The R/W bit of the slave address byte defines the opera- tion to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 12. S t a r t S t o p Slave Address Data A C K SDA Bus Signals from the Slave Signals from the Master 1 0 Slave Address Byte Address A C K A C K S t a r t S t o p Slave Address Data A C K 1 S t a r t SDA Bus Signals from the Slave Signals from the Master X4C105 |
Similar Part No. - X4C105 |
|
Similar Description - X4C105 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
