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X4C105 Datasheet(PDF) 1 Page - Intersil Corporation |
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X4C105 Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 19 page 1 ® FN8124.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X4C105 4K, NOVRAM/EEPROM CPU Supervisor with NOVRAM and Output Ports FEATURES • 4Kbit serial EEPROM —400kHz serial interface speed —16-byte page write mode • One nibble NOVRAM —120ns NOVRAM access speed —AUTOSTORE —Direct/bus access of NOVRAM bits • Four output ports • Operates at 3.3V ± 10% • Low voltage reset when VCC < 3V —3% accurate thresholds available —Output signal shows low voltage condition —Activates NOVRAM AUTOSTORE —Internal block on EEPROM operation • Max EEPROM/NOVRAM nonvolatile write cycle: 5ms • High reliability —1,000,000 endurance cycles —Guaranteed data retention: 100 years • 20-lead TSSOP package DESCRIPTION The low voltage X4C105 combines several functions into one device. The first is a 2-wire, 4Kbit serial EEPROM memory with write protection. A Write Pro- tect (WP) pin provides hardware protection for the upper half of this memory against inadvertent writes. A one nibble NOVRAM is provided and occupies a sin- gle location. This allows access of 4-bits in a single 150ns cycle. This is useful for tracking system opera- tion or process status. The NOVRAM memory is com- pletely isolated from the serial memory section. A low voltage detect circuit activates a RESET pin when VCC drops below 3V. This signal also blocks new read or write operations and initiates a NOVRAM AUTOSTORE. The AUTOSTORE operation is pow- ered by an external capacitor to ensure that the value in the NOVRAM is always maintained in the event of a power failure. The four NOVRAM bits also appear on four separate output pins to allow continuous control of external cir- cuitry, such as ASICs. Intersil EEPROMs are designed and tested for appli- cations requiring extended endurance. Inherent data retention is greater than 100 years. BLOCK DIAGRAM Command Decode and Control Logic HV Generation Timing and Control EEPROM Array Y Decoder Data Register Write Control Logic WP SCL SDA S1 S2 D0 D1 D2 D3 CE OE WE I/O Buffers Control Logic and Timing Static RAM Memory EEPROM Memory VCC VSS RESET Voltage Monitor Power-on Reset Low Voltage Detect CAP Supply O0 O1 O2 O3 Output Buffers and Latches 4Kbits Data Sheet March 18, 2005 |
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