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X28HC64PM-90 Datasheet(PDF) 1 Page - Intersil Corporation |
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X28HC64PM-90 Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 16 page 1 ® FN8109.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X28HC64 64K, 8K x 8 Bit 5 Volt, Byte Alterable EEPROM FEATURES • 70ns access time • Simple byte and page write —Single 5V supply —No external high voltages or VPP control circuits —Self-timed —No erase before write —No complex programming algorithms —No overerase problem • Low power CMOS —40mA active current max. —200µA standby current max. • Fast write cycle times —64-byte page write operation —Byte or page write cycle: 2ms typical —Complete memory rewrite: 0.25 sec. typical —Effective byte write cycle time: 32µs typical • Software data protection • End of write detection —DATA polling —Toggle bit • High reliability —Endurance: 1 million cycles —Data retention: 100 years • JEDEC approved byte-wide pin out DESCRIPTION The X28HC64 is an 8K x 8 EEPROM, fabricated with Intersil’s proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable non- volatile memories, the X28HC64 is a 5V only device. It features the JEDEC approved pinto for byte-wide mem- ories, compatible with industry standard RAMs. The X28HC64 supports a 64-byte page write operation, effectively providing a 32µs/byte write cycle, and enabling the entire memory to be typically written in 0.25 seconds. The X28HC64 also features DATA Polling and Toggle Bit Polling, two methods providing early end of write detection. In addition, the X28HC64 includes a user-optional software data protection mode that further enhances Intersil’s hardware write protect capability. Intersil EEPROMs are designed and tested for appli- cations requiring extended endurance. Inherent data retention is greater than 100 years. PIN CONFIGURATIONS NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 X28HC64 Plastic DIP Flat Pack CERDIP SOIC A6 A5 A4 A3 A2 A1 A0 NC I/O0 A8 A9 A11 NC OE A10 CE I/O7 I/O6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 LCC PLCC (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 3 A 4 A 5 A 6 A 7 A 12 NC VCC NC WE A 8 A 9 A11 OE 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A 2 A 1 A 0 I/O 0 I/O 1 I/O 2 NC VSS NC I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CE A10 X28HC64 X28HC64 11 I/O0 10 A0 14 VSS 9 A1 8 A2 7 A3 6 A4 5 A5 2 A12 28 VCC 12 I/O1 13 I/O2 15 I/O3 4 A6 3 A7 1 16 I/O4 20 CE 22 OE 24 A9 17 I/O5 27 WE 19 I/O7 21 A10 23 A11 25 A8 18 I/O6 26 NC (BOTTOM VIEW) PGA NC X28HC64 TSOP NC NC Bottom View Data Sheet June 1, 2005 |
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