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X5001V8-4.5A Datasheet(PDF) 5 Page - Intersil Corporation |
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X5001V8-4.5A Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 18 page 5 FN8125.0 April 6, 2005 Figure 4. VTRIP Programming Sequence SPI INTERFACE The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the CS/WDI line and asserts RESET output if there is no activity within user select- able time out period. The device also monitors the VCC supply and asserts the RESET if VCC falls below a preset minimum (VTRIP). The device contains an 8-bit watchdog timer register to control the watchdog time out period. The current settings are accessed via the SI and SO pins. All instructions (Table 1) and data are transferred MSB first. Data input on the SI line is latched on the first ris- ing edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. VTRIP Programming Apply 5V to VCC Decrement VCC RESET pin goes active? Measured VTRIP - Desired VTRIP DONE Execute Sequence Reset VTRIP Set VCC = VCC Applied = Desired VTRIP Execute Sequence Set VTRIP New VCC Applied = Old VCC Applied + Error (VCC = VCC - 50mV) Execute Sequence Reset VTRIP New VCC Applied = Old VCC Applied - Error Error < 0 Error = 0 YES NO Error > 0 X5001 |
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