3

FN8130.1

September 16, 2005

Pin Configuration

8 LD SOIC/PDIP

CS

WP

SO

1

2

3

4

RESET/RESET

8

7

6

5

14 LD TSSOP

SO

WP

1

2

3

4

5

6

7

RESET/RESET

SCK

SI

14

13

12

11

10

9

8

NC

NC

X5168/69

SCK

SI

CS

NC

NC

NC

NC

X5168/69

Pin Description

PIN

(SOIC/PDIP)

PIN TSSOP

NAME

FUNCTION

11

CS

Chip Select Input. CS HIGH, deselects the device and the SO output

pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be

in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior

to the start of any operation after power-up, a HIGH to LOW transition on CS is required.

22

SO

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

58

SI

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this

pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),

addresses and data MSB first.

69

SCK

Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge

of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK

changes the data output on the SO pin.

36

WP

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

of the watchdog timer control and the memory write protect bits.

47

Ground

814

Supply Voltage

7

13

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active

enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out

period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-

up at about 1V and remains active for 200ms after the power supply stabilizes.

3-5,10-12

NC

No internal connections

X5168, X5169