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X5643P Datasheet(PDF) 8 Page - Intersil Corporation |
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X5643P Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 19 page  8 FN8135.1 July 18, 2005 While the write is in progress following a status register or EEPROM sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high. OPERATIONAL NOTES The device powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The write enable latch is reset. – The flag bit is reset. – Reset signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: – A WREN instruction must be issued to set the write enable latch. –CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. Figure 6. Read Status Register Sequence Figure 7. Write Enable Latch Sequence 012 345 678 9 10 11 12 13 14 7 654 321 0 Data Out CS SCK SI SO MSB High Impedance Instruction 0 123 456 7 CS SI SCK High Impedance SO X5643, X5645 |
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