X9119TV14I datasheet(4/18 Pages) INTERSIL

Part #	X9119TV14I

Description	Single Supply/Low Power/1024-Tap/2-Wire Bus

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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4 / 18 page

4

FN8162.2

September 15, 2005

Resistor Array Description

The X9119 is comprised of a resistor array. The array

contains, in effect, 1023 discrete resistive segments

that are connected in series (see Figure 1). The

physical ends of each array are equivalent to the fixed

terminals of a mechanical potentiometer (RH and RL

inputs).

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

(RW) output. Within each individual array only one

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

10-bits of the WCR (WCR[9:0]) are decoded to select,

and enable, one of 1024 switches.

The WCR may be written directly. The Data Registers

and the WCR can be read and written by the host

system.

Figure 1. Detailed Potentiometer Block Diagram

Serial Interface Description

SERIAL INTERFACE

The X9119 supports a bidirectional bus oriented

protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9119 will be considered a

slave device in all applications.

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during

SCL LOW periods. SDA state changes during SCL

HIGH are reserved for indicating start and stop

conditions. See Figure 3.

START CONDITION

All commands to the X9119 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH. The X9119 continuously monitors

the SDA and SCL lines for the start condition and will

not respond to any command until this condition is

met. See Figure 3.

STOP CONDITION

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH. See Figure 3.

ACKNOWLEDGE

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

Serial Data Path

From Interface

Register 0

Serial

Bus

Input

Parallel

Bus

Input

Counter

Register

RH

RL

R

W

10

C

O

U

N

T

E

R

D

E

C

O

D

E

If WCR = 000[HEX] then RW = RL

If WCR = 3FF[HEX] then RW = RH

Wiper

(WCR)

(DR0)

Circuitry

Register 1

(DR1)

Register 2

(DR2)

Register 3

(DR3)

X9119

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