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X5165V14I-4.5A Datasheet(PDF) 5 Page - Intersil Corporation |
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X5165V14I-4.5A Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 20 page 5 FN8128.1 May 16, 2005 SPI Serial Memory The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 7). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle. Status Register The RDSR instruction provides access to the Status Register. The Status Register may be read at any time, even during a Write Cycle. The Status Register is formatted as follows: The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress. 7 6 5 4 3 210 WPEN FLB WD1 WD0 BL1 BL0 WEL WIP TABLE 1. INSTRUCTION SET INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations) SFLB 0000 0000 Set Flag Bit WRDI/RFLB 0000 0100 Reset the Write Enable Latch/Reset Flag Bit RSDR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits) READ 0000 0011 Read Data from Memory Array Beginning at Selected Address WRITE 0000 0010 Write Data to Memory Array Beginning at Selected Address NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. TABLE 2. BLOCK PROTECT MATRIX WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER WEL WPEN WP# PROTECTED BLOCK UNPROTECTED BLOCK WPEN, BL0, BL1, WD0, WD1 0 X X Protected Protected Protected 1 1 0 Protected Writable Protected 1 0 X Protected Writable Writable 1 X 1 Protected Writable Writable X5163, X5165 |
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