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X5165V14T1 Datasheet(PDF) 6 Page - Intersil Corporation |
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X5165V14T1 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 20 page  6 FN8128.1 May 16, 2005 The Write Enable Latch (WEL) bit indicates the Status of the Write Enable Latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time Out Period. These nonvolatile bits are programmed with the WRSR instruction. The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The Flag bit is automatically reset upon power- up. This flag can be used by the system to determine whether a reset occurs as a result of a watchdog time out or power failure. The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide an In-Circuit Programmable ROM function (Table 2). WP is LOW and WPEN bit programmed HIGH disables all Status Register Write Operations. In Circuit Programmable ROM Mode This mechanism protects the block lock and Watchdog bits from inadvertent corruption. In the locked state (Programmable ROM Mode) the WP pin is LOW and the nonvolatile bit WPEN is “1”. This mode disables nonvolatile writes to the device’s Status Register. Setting the WP pin LOW while WPEN is a “1” while an internal write cycle to the Status Register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the Status Register. STATUS REGISTER BITS ARRAY ADDRESSES PROTECTED BL1 BL0 X516X 0 0 None 0 1 $0600-$07FF 1 0 $0400-$07FF 1 1 $0000-$07FF STATUS REGISTER BITS WATCHDOG TIME OUT (TYPICAL) WD1 WD0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled STATUS REGISTER BITS WATCHDOG TIME OUT (TYPICAL) WD1 WD0 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 543 21 0 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 16 BIT ADDRESS 15 14 13 3 2 1 0 FIGURE 5. READ EEPROM ARRAY SEQUENCE X5163, X5165 |
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