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X9221AUSZ Datasheet(PDF) 3 Page - Intersil Corporation |
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X9221AUSZ Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 15 page 3 FN8163.1 September 14, 2005 PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9221A. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical val- ues, refer to the guidelines for calculating typical val- ues on the bus pull-up resistors graph. Address The Address inputs are used to set the least signifi- cant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9221A Potentiometer Pins VH/RH(VH0/RH0-VH1/RH1), VL/RL (VL0/RL0-VL1/RL1) The VH/RH and VL/RL inputs are equivalent to the ter- minal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0-VW1/RW1) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. PIN CONFIGURATION PIN NAMES PRINCIPLES OF OPERATION The X9221A is a highly integrated microcircuit incor- porating two resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9221A supports a bidirectional bus oriented pro- tocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and pro- vide the clock for both transmit and receive operations. Therefore, the X9221A will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9221A are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9221A continu- ously monitors the SDA and SCL lines for the start condition, and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop con- dition, which is a LOW to HIGH transition of SDA while SCL is HIGH. VW0/RW0 VL0/RL0 VH0/RL0 A0 A2 VW1/RW1 VL1/RL1 VH1/RH1 SDA VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC RES RES RES A1 A3 SCL RES RES RES DIP/SOIC X9221A Symbol Description SCL Serial Clock SDA Serial Data A0–A3 Address VH0/RH0-VH1/RH1, VL0/RH0-VL1/RL0 Potentiometers (terminal equivalent) VW0/RW0-VW1/RW1 Potentiometers (wiper equivalent) RES Reserved (Do not connect) X9221A |
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