1

®

FN8167.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

X9252

Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface

Quad Digitally-Controlled (XDCP™)

Potentiometer

The X9252 integrates 4 digitally controlled potentiometers

(XDCP) on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented

using 255 resistive elements in a series array. Between each

pair of elements are tap points connected to wiper terminals

through switches. The position of each wiper on the array is

controlled by the user through the Up/Down (U/D) or 2-wire

bus interface. The wiper of each potentiometer has an

associated volatile Wiper Counter Register (WCR) and four

non-volatile Data Registers (DRs) that can be directly written

to and read by the user. The contents of the WCR controls

the position of the wiper on the resistor array through the

switches. At power-up, the device recalls the contents of the

default data registers DR00, DR10, DR20, DR30, to the

corresponding WCR.

Each DCP can be used as a three-terminal potentiometer or

as a two terminal variable resistor in a wide variety of

applications including the programming of bias voltages, the

implementation of ladder networks, and three resistor

programmable networks.

Features

• Quad Solid State Potentiometer

• 256 Wiper Tap Points-0.4% Resolution

• 2-Wire Serial Interface for Write, Read, and Transfer

Operations of the Potentiometer

• Up/Down Interface for Individual Potentiometers

• Wiper Resistance: 40

Ω Typical

• Non-Volatile Storage of Wiper Positions

• Power On Recall. Loads Saved Wiper Position on Power-

Up.

• Standby Current < 20µA Max

• Maximum Wiper Current: 3mA

•2.8k

Ω,10kΩ, 50kΩ, 100kΩ Version of Total Pot Resistance

• Endurance: 100, 000 Data Changes per Bit per Register

• 100 yr. Data Retention

• 24 Ld TSSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinout

X9252

(24 LD TSSOP)

TOP VIEW

1

2

3

4

5

6

7

14

20

19

18

17

16

15

X9252

DS0

DS1

A0

U/D

SCL

CS

8

9

10

13

WP

A2

11

12

SDA

A1

24

23

22

21

Data Sheet

September 14, 2005