2

FN8167.1

September 14, 2005

Functional Diagram

Ordering Information

PART NUMBER

PART MARKING

TEMP RANGE (°C)

PACKAGE

X9252YV24I-2.7

X9252YV G

2.8

-40 to 85

24 Ld TSSOP (4.4mm)

X9252YV24IZ-2.7 (Note)

X9252YV Z G

-40 to 85

24 Ld TSSOP (4.4mm) (Pb-free)

X9252WS24I-2.7

X9252WS G

10

-40 to 85

24 Ld SOIC (300 mil)

X9252WS24IZ-2.7 (Note)

X9252WS Z G

-40 to 85

24 Ld SOIC (300 mil) (Pb-Free)

X9252WV24I-2.7

X9252WV G

-40 to 85

24 Ld TSSOP (4.4mm)

X9252WV24IZ-2.7 (Note)

X9252WV Z G

-40 to 85

24 Ld TSSOP (4.4mm) (Pb-free)

X9252US24I-2.7

50

-40 to 85

24 Ld SOIC (300 mil)

X9252US24IZ-2.7 (Note)

X9252US Z G

-40 to 85

24 Ld SOIC (300 mil) (Pb-Free)

X9252UV24I-2.7

X9252UV G

-40 to 85

24 Ld TSSOP (4.4mm)

X9252UV24IZ-2.7 (Note)

X9252UV Z G

-40 to 85

24 Ld TSSOP (4.4mm) (Pb-free)

X9252TS24I-2.7

100

-40 to 85

24 Ld SOIC (300 mil)

X9252TS24IZ-2.7 (Note)

X9252TS Z G

-40 to 85

24 Ld SOIC (300 mil) (Pb-Free)

X9252TV24I-2.7

X9252TV G

-40 to 85

24 Ld TSSOP (4.4mm)

X9252TV24IZ-2.7 (Note)

X9252TV Z G

-40 to 85

24 Ld TSSOP (4.4mm) (Pb-free)

Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

POWER UP,

INTERFACE

CONTROL

AND

2-Wire

DCP0

A1

SDA

SCL

CS

U/D

A2

DS0

DS1

WP

WCR0

DR00

DR01

DR02

DR03

DCP1

WCR1

DR10

DR11

DR12

DR13

DCP2

WCR2

DR20

DR21

DR22

DR23

DCP3

WCR3

DR30

DR31

DR32

DR33

A0

Interface

Up-Down

Interface

STATUS

Pin Descriptions

TSSOP PIN

SYMBOL

BRIEF DESCRIPTION

1

DS0

DCP select for Up/Down interface.

2

A0

Device address for 2-wire bus.

3

RW3

Wiper terminal of DCP3.

4

RH3

High terminal of DCP3.

5

RL3

Low terminal of DCP3.

X9252